利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

80 条记录 (耗时 0.025 秒)

    Majority voter circuits and semiconductor devices including the same
    21.
    发明申请
    Majority voter circuits and semiconductor devices including the same 有权
    多数选民电路和半导体器件包括相同

    公开(公告)号：US20080001626A1

    公开(公告)日：2008-01-03

    申请号：US11819600

    申请日：2007-06-28

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    IPC分类号： H03K19/23

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

    Semiconductor memory device and method of controlling the same
    22.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08649238B2

    公开(公告)日：2014-02-11

    申请号：US13078218

    申请日：2011-04-01

    申请人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

    摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

    Data write training method
    23.
    发明授权
    Data write training method 有权
    数据写入训练方法

    公开(公告)号：US08593901B2

    公开(公告)日：2013-11-26

    申请号：US13868425

    申请日：2013-04-23

    申请人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

    摘要翻译： 实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据 数据线。 在不附加训练命令的情况下执行发送第一写入数据。

    Majority voter circuits and semiconductor devices including the same
    26.
    发明授权
    Majority voter circuits and semiconductor devices including the same 有权
    多数选民电路和半导体器件包括相同

    公开(公告)号：US07688102B2

    公开(公告)日：2010-03-30

    申请号：US11819600

    申请日：2007-06-28

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    IPC分类号： H03K19/003

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

    SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT
    28.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT 有权
    具有节能效果的半导体存储器件

    公开(公告)号：US20100329041A1

    公开(公告)日：2010-12-30

    申请号：US12797791

    申请日：2010-06-10

    申请人： Young-Soo SOHN ,  Kwang-IL Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    发明人： Young-Soo SOHN ,  Kwang-IL Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    IPC分类号： G11C7/10 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/2227 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

    摘要翻译： 半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。 存储单元阵列包括多个存储单元，并被配置为存储数据。 当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号 设备。 数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

    TRANSMITTING/RECEIVING METHODS AND SYSTEMS FOR DC BALANCE ENCODED DATA INCLUDING SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES
    29.
    发明申请
    TRANSMITTING/RECEIVING METHODS AND SYSTEMS FOR DC BALANCE ENCODED DATA INCLUDING SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES 有权
    用于直流平衡编码数据的发送/接收方法和系统，包括同时开关噪声减少前提

    公开(公告)号：US20070229320A1

    公开(公告)日：2007-10-04

    申请号：US11693264

    申请日：2007-03-29

    申请人： Seung-Jun Bae ,  Seong-Jin Jang

    发明人： Seung-Jun Bae ,  Seong-Jin Jang

    IPC分类号： H03M7/00

    CPC分类号： H03M5/145

    摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

    摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

    Data output buffer and memory device
    30.
    发明授权
    Data output buffer and memory device 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US08553471B2

    公开(公告)日：2013-10-08

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。