公开(公告)号：US06563750B2

公开(公告)日：2003-05-13

申请号：US10134521

申请日：2002-04-30

申请人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

发明人： Hiroshi Otori ,  Hiroki Fujisawa ,  Minoru Ebihara ,  Seiji Narui ,  Masanori Isoda ,  Akira Ohta

IPC分类号： G11C700

CPC分类号： G11C29/70 ,  G11C5/025 ,  G11C5/063

摘要： Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.

摘要翻译： 每个具有用于根据阈值电压差存储信息的电可编程电保险丝和地址比较器的排气单元（UNITb）设置在第二区域中，并且每个具有激光熔丝和地址比较器的释放单元（UNITa）设置在 第一个区域。 两个区域沿着每个比较器的地址信号布线彼此相邻，并且地址信号布线线性布置。 即使电保险丝和激光熔丝被共存用于释放地址存储，也可以基于在地址信号布线的方向上延伸的大小来调整由于它们的配置之间的差异造成的片外占用面积之间的差异， 并且可以从布局的观点最大限度地抑制片上占用面积的增加。

公开(公告)号：US08508969B2

公开(公告)日：2013-08-13

申请号：US13533896

申请日：2012-06-26

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C5/06

CPC分类号： G11C11/401 ,  G11C5/025 ,  G11C5/06 ,  G11C8/18 ,  G11C11/4097

摘要： A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.

摘要翻译： 一种器件包括：第一读出放大器阵列，包括以第一方向布置的多个第一读出放大器，每个第一读出放大器包括第一和第二节点;沿与第一方向交叉的第二方向延伸的多个第一全局位线; 所述第一全局位线沿所述第一方向布置在所述第一读出放大器阵列的左侧，使得所述第一全局位线可操作地连接到所述第一读出放大器中的相关联的第一读出放大器的第一节点，以及多个第二 全局位线沿第二方向延伸，第二全局位线沿第一方向排列在第一读出放大器阵列的右侧，使得第二全局位线可操作地连接到相关联的一个的第二节点 第一感测放大器。

公开(公告)号：US20120300529A1

公开(公告)日：2012-11-29

申请号：US13533896

申请日：2012-06-26

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C5/06

CPC分类号： G11C11/401 ,  G11C5/025 ,  G11C5/06 ,  G11C8/18 ,  G11C11/4097

摘要： A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.

摘要翻译： 一种器件包括：第一读出放大器阵列，包括以第一方向布置的多个第一读出放大器，每个第一读出放大器包括第一和第二节点;沿与第一方向交叉的第二方向延伸的多个第一全局位线; 所述第一全局位线沿所述第一方向布置在所述第一读出放大器阵列的左侧，使得所述第一全局位线可操作地连接到所述第一读出放大器中的相关联的第一读出放大器的第一节点，以及多个第二 全局位线沿第二方向延伸，第二全局位线沿第一方向排列在第一读出放大器阵列的右侧，使得第二全局位线可操作地连接到相关联的一个的第二节点 第一感测放大器。

公开(公告)号：US07903489B2

公开(公告)日：2011-03-08

申请号：US11763772

申请日：2007-06-15

申请人： Takeshi Ohgami ,  Seiji Narui

发明人： Takeshi Ohgami ,  Seiji Narui

IPC分类号： G11C7/02

CPC分类号： H01L27/10897 ,  H01L27/0207

摘要： A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.

摘要翻译： 本发明的半导体器件包括由第一晶体管和第二晶体管组成的对晶体管。 该对晶体管以行方向排列成重复图案。 第一晶体管和第二晶体管彼此相互关联，使得一个晶体管的漏极连接到另一个晶体管的栅极。 第一晶体管的栅极和第二晶体管的栅极在行方向上偏移。 第一晶体管和第二晶体管处于对角位置关系。

公开(公告)号：US20110026292A1

公开(公告)日：2011-02-03

申请号：US12805015

申请日：2010-07-07

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C5/06

CPC分类号： G11C11/401 ,  G11C5/025 ,  G11C5/06 ,  G11C8/18 ,  G11C11/4097

摘要： To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

摘要翻译： 包括存储器垫，每个存储器堆包括放大全局位线之间的电位差的读出放大器，连接到全局位线的多个分层开关以及经由分层开关连接到全局位线的多个局部位线，以及 激活层级交换机的控制电路。 控制电路激活位于沿着全局位线与读出放大器相同距离的分层开关。 根据本发明，由于无论选择的局部位线如何，寄生CR分布常数均无差异，可以防止感测灵敏度下降。

公开(公告)号：US20090034353A1

公开(公告)日：2009-02-05

申请号：US12222105

申请日：2008-08-01

申请人： Seiji Narui ,  Takeshi Ohgami

发明人： Seiji Narui ,  Takeshi Ohgami

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/063

摘要： A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat.

摘要翻译： 一种半导体存储器件包括多个阵列排列的阵列，每个阵列包括存储电荷作为信息的多个存储单元和多个电源线，每条线的一端共同连接到内部电源， 增加从外部电源供给的电压。 电源线在形成多个垫的区域中沿给定的方向延伸，并且多个电源线的每条线的另一端在边缘垫上共同连接。

公开(公告)号：US20080012107A1

公开(公告)日：2008-01-17

申请号：US11822265

申请日：2007-07-03

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

摘要翻译： 公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧 的芯片以及。 四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。 用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

公开(公告)号：US20080008013A1

公开(公告)日：2008-01-10

申请号：US11763772

申请日：2007-06-15

申请人： Takeshi OHGAMI ,  Seiji Narui

发明人： Takeshi OHGAMI ,  Seiji Narui

IPC分类号： G11C16/28

CPC分类号： H01L27/10897 ,  H01L27/0207

摘要： A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.

摘要翻译： 本发明的半导体器件包括由第一晶体管和第二晶体管组成的对晶体管。 该对晶体管以行方向排列成重复图案。 第一晶体管和第二晶体管彼此相互关联，使得一个晶体管的漏极连接到另一个晶体管的栅极。 第一晶体管的栅极和第二晶体管的栅极在行方向上偏移。 第一晶体管和第二晶体管处于对角位置关系。

公开(公告)号：US20140104919A1

公开(公告)日：2014-04-17

申请号：US14107983

申请日：2013-12-16

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C11/401

CPC分类号： G11C11/401 ,  G11C5/025 ,  G11C5/06 ,  G11C8/18 ,  G11C11/4097

摘要： A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.

摘要翻译： 用于感测开放位线动态随机存取存储器中的数据的方法包括激活第一存储器堆的第一存储块中的字线以将电荷从存储器单元传送到第一子位线，第一存储器衬垫位于第二存储器块之间 存储器垫和第三存储器垫，激活对应于第一存储器块的第一层次开关以将电荷从第一子位线传送到第一存储器堆的全局位线，以及激活对应于第一存储器块中的第二存储器块的第二层次开关 将子位线连接到第二存储器垫的全局位线，第一存储器块和第二存储器块与位于第一存储器垫和第二存储器垫之间的第一读出放大器阵列等距。

公开(公告)号：US08374044B2

公开(公告)日：2013-02-12

申请号：US12805014

申请日：2010-07-07

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C7/06

CPC分类号： G11C7/227 ,  G11C11/4091 ,  G11C11/4097

摘要： A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat.

摘要翻译： 半导体器件包括全局位线，比全局位线短的虚拟全局位线，放大全局位线和虚拟全局位线之间的电位差的读出放大器，每个存储块包括 经由分层交换机连接到全局位线的分层交换机和局部位线，包括虚拟分层交换机和虚拟本地位线的虚拟存储器模块，虚拟本地位线线经由虚拟层次结构连接到虚拟全局位线 开关和控制电路，其激活层级开关和虚拟层级开关中的任何一个。 利用该配置，可以在位于边缘的存储器垫和另一个存储器垫之间获得相同的存储器容量。