公开(公告)号：US08103997B2

公开(公告)日：2012-01-24

申请号：US12426492

申请日：2009-04-20

申请人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

发明人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.

摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

公开(公告)号：US20100269083A1

公开(公告)日：2010-10-21

申请号：US12426492

申请日：2009-04-20

申请人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

发明人： Debjit Sinha ,  Soroush Abbaspour ,  Adil Bhanji ,  Jeffrey M. Ritzinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.

摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。

公开(公告)号：US20080250370A1

公开(公告)日：2008-10-09

申请号：US11733058

申请日：2007-04-09

申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

公开(公告)号：US07739640B2

公开(公告)日：2010-06-15

申请号：US11622979

申请日：2007-01-12

申请人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

发明人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

公开(公告)号：US07594209B2

公开(公告)日：2009-09-22

申请号：US11741042

申请日：2007-04-27

申请人： Soroush Abbaspour ,  Harry J. Beatty, III

发明人： Soroush Abbaspour ,  Harry J. Beatty, III

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is selected with its respective fan-out gates, interconnects attached to the primitive gate's output and interconnects attached to the output of each respective fan-out gate are determined. Using a metric, it is determined if the Miller capacitance effect of a CMOS gate on timing of its fan-out gate and interconnect timing is significant for each fan-out gate. If yes, the gate is replaced with a nonlinear driver model. If no, the gate is replaced with a fixed or dynamic capacitance. Next, if at least one of the fan-out gates is replaced with the nonlinear driver model, the primitive gate is likewise replaced with its corresponding nonlinear model as well. Then, a nonlinear timing simulation is performed on the circuit to generate voltage waveforms at the output of the primitive gate and the input of its fan-out gates that incorporate the effect of the Miller capacitance. However, if none of the fan-out gates are replaced with the nonlinear driver model, a conventional gate and interconnect timing analysis is preferably performed.

摘要翻译： 通过结合米勒电容对定时的影响，对包含栅极及其各自互连的电路执行静态时序分析的方法。 通过其各自的扇出门选择原始门，确定连接到原始门的输出的互连和连接到每个相应的扇出输出门的输出的互连。 使用度量，确定CMOS门极的米勒电容效应是否对于扇出门和互连时序的定时对于每个扇出门是重要的。 如果是，门被替换为非线性驱动器模型。 如果不是，则门被替换为固定或动态电容。 接下来，如果用非线性驱动器模型代替扇出门中的至少一个，则基本门也同样被其对应的非线性模型所取代。 然后，在电路上执行非线性时序仿真，以在原始栅极的输出端和其扇出门的输入端产生并入米勒电容效应的电压波形。 然而，如果不用非线性驱动器模型替换扇出门，则优选地执行常规的栅极和互连时序分析。

公开(公告)号：US20080270960A1

公开(公告)日：2008-10-30

申请号：US11741042

申请日：2007-04-27

申请人： Soroush Abbaspour ,  Harry J. Beatty

发明人： Soroush Abbaspour ,  Harry J. Beatty

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

摘要： A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is selected with its respective fan-out gates, interconnects attached to the primitive gate's output and interconnects attached to the output of each respective fan-out gate are determined. Using a metric, it is determined if the Miller capacitance effect of a CMOS gate on timing of its fan-out gate and interconnect timing is significant for each fan-out gate. If yes, the gate is replaced with a nonlinear driver model. If no, the gate is replaced with a fixed or dynamic capacitance. Next, if at least one of the fan-out gates is replaced with the nonlinear driver model, the primitive gate is likewise replaced with its corresponding nonlinear model as well. Then, a nonlinear timing simulation is performed on the circuit to generate voltage waveforms at the output of the primitive gate and the input of its fan-out gates that incorporate the effect of the Miller capacitance. However, if none of the fan-out gates are replaced with the nonlinear driver model, a conventional gate and interconnect timing analysis is preferably performed.

摘要翻译： 通过结合米勒电容对定时的影响，对包含栅极及其各自互连的电路执行静态时序分析的方法。 通过其各自的扇出门选择原始门，确定连接到原始门的输出的互连和连接到每个相应的扇出输出门的输出的互连。 使用度量，确定CMOS门极的米勒电容效应是否对于扇出门和互连时序的定时对于每个扇出门是重要的。 如果是，门被替换为非线性驱动器模型。 如果不是，则门被替换为固定或动态电容。 接下来，如果用非线性驱动器模型代替扇出门中的至少一个，则基本门也同样被其对应的非线性模型所取代。 然后，在电路上执行非线性时序仿真，以在原始栅极的输出端和其扇出门的输入端产生并入米勒电容效应的电压波形。 然而，如果不用非线性驱动器模型替换扇出门，则优选地执行常规的栅极和互连时序分析。

公开(公告)号：US20110016442A1

公开(公告)日：2011-01-20

申请号：US12503924

申请日：2009-07-16

申请人： Soroush Abbaspour ,  Debjit Sinha

发明人： Soroush Abbaspour ,  Debjit Sinha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.

摘要翻译： 支持多层次级别的抽象模型被输入到分层IC芯片设计的广义静态时序分析中，以分析和优化包含多个宏抽象的芯片集成的电路的设计。 为内部抽象互连段合成的电气网络每宏执行一次，并应用于IC芯片设计中的宏抽象模型的多个实例。 合成电网是阻性电容或电阻感应电容网络或其组合。 然后使用合成的电气网络来匹配网络的脉冲响应传递函数和抽象互连段的时序模型。 该网络与连接到宏主要输出的外部互连段的电气寄生线缝合。 然后在网络拼接之前对外部互连的电寄生效应进行各种模型顺序减少。 在最终网络上执行静态时序分析。

公开(公告)号：US07814448B2

公开(公告)日：2010-10-12

申请号：US11733058

申请日：2007-04-09

申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

公开(公告)号：US07552412B2

公开(公告)日：2009-06-23

申请号：US11274556

申请日：2005-11-15

申请人： Soroush Abbaspour ,  Gary S. Ditlow ,  Chandramouli V. Kashyap ,  Ruchir Puri

发明人： Soroush Abbaspour ,  Gary S. Ditlow ,  Chandramouli V. Kashyap ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

摘要翻译： 电路设计方法，计算机程序产品和芯片设计系统体现了该方法。 从电路设计中选择静态时序分析（STA）的门。 为所选择的门确定初始性能特征（例如负载和转换转换）。 从初始性能特性确定栅极的电荷等效有效电容（CQeff）。 在使用CQeff作为所选择的栅极的有效负载的栅极的单次通过中确定栅极延迟。 可选地，如果总栅极负载电容（Ctot）超过CQeff小于最小值，则确定有效电容（Ceff）并用于确定栅极延迟。

公开(公告)号：US20060150133A1

公开(公告)日：2006-07-06

申请号：US11274556

申请日：2005-11-15

申请人： Soroush Abbaspour ,  Gary Ditlow ,  Chandramouli Kashyap ,  Ruchir Puri

发明人： Soroush Abbaspour ,  Gary Ditlow ,  Chandramouli Kashyap ,  Ruchir Puri

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

摘要翻译： 电路设计方法，计算机程序产品和芯片设计系统体现了该方法。 从电路设计中选择静态时序分析（STA）的门。 为所选择的门确定初始性能特征（例如负载和转换转换）。 从初始性能特性确定栅极的电荷等效有效电容（C QEff）。 门使用C QEff 作为所选择的门的有效负载，在门的单次通过中确定门延迟。 可选地，如果总栅极负载电容（C SUB）大于最小值，则有效电容（C eff）为 确定并用于确定门延迟。