公开(公告)号：US20060141790A1

公开(公告)日：2006-06-29

申请号：US11321848

申请日：2005-12-28

申请人： Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76819 ,  C09G1/02 ,  H01L21/31053

摘要： In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

公开(公告)号：US20050255654A1

公开(公告)日：2005-11-17

申请号：US11103069

申请日：2005-04-11

申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

公开(公告)号：US20050075052A1

公开(公告)日：2005-04-07

申请号：US10947458

申请日：2004-09-22

申请人： Kwang-Bok Kim ,  Jae-Kwang Choi ,  Yong-Sun Ko ,  Chang-Ki Hong ,  Kyung-Hyun Kim ,  Jae-Dong Lee

发明人： Kwang-Bok Kim ,  Jae-Kwang Choi ,  Yong-Sun Ko ,  Chang-Ki Hong ,  Kyung-Hyun Kim ,  Jae-Dong Lee

IPC分类号： H01L21/304 ,  B24B37/04 ,  B24B49/16 ,  B24B57/02 ,  C09G1/02 ,  B24B1/00 ,  B24B7/19

CPC分类号： C09G1/02 ,  B24B37/044 ,  B24B49/16 ,  B24B57/02

摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

摘要翻译： 为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。 第一和第二种浆料是不同的。 例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。 此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

公开(公告)号：US20100147799A1

公开(公告)日：2010-06-17

申请号：US12711344

申请日：2010-02-24

申请人： Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： C23F1/00

CPC分类号： H01L21/76819 ,  C09G1/02 ,  H01L21/31053

摘要： In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

摘要翻译： 在一个实施方案中，一种用于具有第一层和阶梯部分的基材的化学机械抛光方法。 第一层的表面位于台阶部的上表面的上方。 通过使用具有自停特性的第一浆料组合物在第一层上进行用于选择性去除台阶部分的抛光工艺，使得第一层变成具有基本平坦表面的第二层。 使用不具有自停特性的第二浆料组合物进行第二抛光处理，直到阶梯部分的上表面露出。

公开(公告)号：US07709319B2

公开(公告)日：2010-05-04

申请号：US11450269

申请日：2006-06-12

申请人： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10852

摘要： Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

摘要翻译： 提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。 电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。 虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。 然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

公开(公告)号：US07579284B2

公开(公告)日：2009-08-25

申请号：US11482773

申请日：2006-07-10

申请人： Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L21/311

CPC分类号： C09K13/04 ,  H01L21/32134

摘要： Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.

摘要翻译： 本发明的示例性实施例涉及一种蚀刻溶液，使用该方法形成图案的方法，使用该蚀刻溶液的多栅极氧化物层的制造方法以及使用其制造闪存器件的方法。 本发明的其它示例性实施例涉及在多晶硅层和氧化物层之间具有蚀刻选择性的蚀刻溶液，使用其使用蚀刻溶液形成图案的方法，使用该栅极氧化物层的方法 以及使用其制造闪存器件的方法。 包含在水中混合的体积比为约1:2至约1:10的过氧化氢（H 2 O 2）和氢氧化铵（NH 4 OH）的蚀刻溶液。 在形成图案的方法和制造多栅极氧化物层和闪存器件的方法中，可以在衬底上形成多晶硅层。 可以在多晶硅层上形成包括露出多晶硅层的开口的绝缘层图案。 可以使用蚀刻溶液蚀刻由绝缘层图案暴露的多晶硅层。 可以使用蚀刻溶液在衬底上形成多晶硅层图案。

公开(公告)号：US20080042240A1

公开(公告)日：2008-02-21

申请号：US11976251

申请日：2007-10-23

申请人： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L29/00

CPC分类号： H01L27/10894 ,  H01L27/10852

摘要： Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

摘要翻译： 提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。 电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。 虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。 然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

公开(公告)号：US20060115950A1

公开(公告)日：2006-06-01

申请号：US11284678

申请日：2005-11-22

申请人： Kwang-Bok Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Kwang-Bok Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L21/3212

摘要： A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.

摘要翻译： 形成电容器的方法可以包括在绝缘层和其外部的沟槽中的金属层上形成保护层。 可以使用化学机械抛光（CMP）工艺将保护层的表面和下面的金属层平坦化，以使沟槽外部的绝缘层的表面露出。 还公开了相关结构。

公开(公告)号：US20060105686A1

公开(公告)日：2006-05-18

申请号：US11260902

申请日：2005-10-28

申请人： Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： B24B1/00 ,  B24D17/00

CPC分类号： B24B37/16

摘要： A platen structure of a polishing apparatus for semiconductor wafer and a method for exchanging a polishing pad affixed to the same are provided in which the polishing pad supported by the platen is exchanged with convenience within a short time. The platen structure of the polishing apparatus in which the polishing pad attached to the platen of the polishing apparatus comprises a pad plate to which the polishing pad for polishing a wafer is attached, and a platen body combined with the pad plate and having at least one vacuum hole formed thereto to provide a vacuum passage.

摘要翻译： 提供了一种用于半导体晶片的抛光装置的压板结构和用于更换固定在其上的抛光垫的方法，其中在短时间内方便地更换由压板支撑的抛光垫。 抛光装置的压板结构，其中安装在抛光装置的压板上的抛光垫包括一个垫板，用于抛光晶片的抛光垫被安装到该垫板上，以及压板体与该焊盘板组合并具有至少一个 形成真空孔以提供真空通道。

公开(公告)号：US20050272348A1

公开(公告)日：2005-12-08

申请号：US11122918

申请日：2005-05-03

申请人： Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

发明人： Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC分类号： H01L21/304 ,  B24B37/04 ,  B24B49/00

CPC分类号： B24D7/14 ,  B24B37/10 ,  B24B37/20

摘要： An apparatus for polishing a wafer is provided. The apparatus comprises a polishing pad for polishing the wafer. The polishing pad is divided into multiple portions that are rotated in a substantially same direction. At least one of the portions of the polishing pad is adapted to rotate at a speed different than the other portions. A driving unit is also provided for moving the polishing pad. A polishing head is employed for maintaining the side of the wafer to be polished engaged with the polishing pad, for contacting the polished surface of the wafer with the polishing pad, and for rotating the wafer.

摘要翻译： 提供了一种用于抛光晶片的设备。 该装置包括用于抛光晶片的抛光垫。 抛光垫被分成沿基本相同方向旋转的多个部分。 抛光垫的至少一部分适于以与其它部分不同的速度旋转。 还提供用于移动抛光垫的驱动单元。 采用抛光头来保持要抛光的晶片的侧面与抛光垫相接合，以使晶片的抛光表面与抛光垫接触，并使晶片转动。