摘要:
A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.
摘要:
In a first aspect, a method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.
摘要:
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要:
A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.
摘要:
Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer.
摘要:
Underfill flow guide structures and methods of using the same are provided with a module. The method includes mounting bumps on a substrate. The method also includes forming underfill flow guide structures on the substrate by patterning wires with an overlay of hard substance. The underfill flow guide structures are integrated with the substrate and formed between adjacent bumps. The underfill flow guide structures are further formed to uniformly guide underfill along the substrate during capillary underfill processing.
摘要:
A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.
摘要:
A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.
摘要:
A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.
摘要:
A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.