利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

212 条记录 (耗时 0.03 秒)

    Semiconductor chips with reduced stress from underfill at edge of chip
    23.
    发明授权
    Semiconductor chips with reduced stress from underfill at edge of chip 失效
    半导体芯片在芯片边缘的底层填料中的应力减小

    公开(公告)号：US07777339B2

    公开(公告)日：2010-08-17

    申请号：US11830228

    申请日：2007-07-30

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    摘要： Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    摘要翻译： 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。

    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
    26.
    发明申请
    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP 失效
    具有降低应力的半导体芯片

    公开(公告)号：US20090032929A1

    公开(公告)日：2009-02-05

    申请号：US11830228

    申请日：2007-07-30

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L23/24 ,  H01L21/00

    CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    摘要： Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    摘要翻译： 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。

    WAFER EDGE CONDITIONING FOR THINNED WAFERS
    28.
    发明申请
    WAFER EDGE CONDITIONING FOR THINNED WAFERS 有权
    用于薄膜波纹的边缘调节

    公开(公告)号：US20120241916A1

    公开(公告)日：2012-09-27

    申请号：US13053803

    申请日：2011-03-22

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    IPC分类号： H01L29/02 ,  H01L21/302

    CPC分类号： H01L21/02021

    摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

    摘要翻译： 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。