公开(公告)号：US20180374765A1

公开(公告)日：2018-12-27

申请号：US16057826

申请日：2018-08-08

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chien-Hao Chen ,  Chien-Wei Huang ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC分类号： H01L21/66

摘要： A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.