公开(公告)号：US20170039311A1

公开(公告)日：2017-02-09

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract translation: 一种用于设计半导体布局结构的方法包括以下步骤。 接收包括至少第一活动特征的第一活动特征组，并且第一活动特征包括第一信道长度。 引入一对第一虚拟特征以形成第一细胞图案。 第一虚拟特征包括第一虚拟宽度。 在第一活动特征组和第一虚拟特征之一之间限定第一间隔宽度，并且在第一活动特征组和第二虚拟特征之间限定第三间隔宽度。 第一单元图案包括第一单元宽度和第一多段间距，并且第一单元宽度是第一间距的倍数。 至少由计算机辅助设计工具执行第一活动特征组的接收和第一虚拟特征的引入。