公开(公告)号：US20050144214A1

公开(公告)日：2005-06-30

申请号：US10745712

申请日：2003-12-24

申请人： Ramyanshu Datta ,  Robert Montoye

发明人： Ramyanshu Datta ,  Robert Montoye

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/544

CPC分类号： G06F5/012 ,  G06F7/5443

摘要： A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and a group of data signals to generate a group of first intermediate signals. The coarse shift stage receives a second set of shift signals and the group of first intermediate signals to generate a group of second intermediate signals and their complement signals. The large shift stage and the coarse shift stage are executed within a first single processor cycle. The negate stage receives a complement decision signal and the group of second intermediate signals along with their complement signals to generate a group of third intermediate signals. Finally, the fine shift stage receives a third set of shift signals and the group of third intermediate signals to generate a group of output signals. The negate stage and the fine shift stage are executed within a second single processor cycle.

摘要翻译： 公开了一种融合乘法加法器电路内的低功率移相和无效单元。 移位和否定单元包括大的移位阶段，粗调班级，否定阶段和精细班级。 大移位级接收第一组移位信号和一组数据信号以产生一组第一中间信号。 粗移位级接收第二组移位信号和第一中间信号组，以产生一组第二中间信号及其补码信号。 在第一单个处理器周期内执行大移位级和粗移位级。 否定阶段接收补码判定信号和第二中间信号组及其补码信号以产生一组第三中间信号。 最后，精细移位级接收第三组移位信号和第三中间信号组，以产生一组输出信号。 否定阶段和精细转换阶段在第二个单个处理器周期内执行。

公开(公告)号：US20050102345A1

公开(公告)日：2005-05-12

申请号：US10702989

申请日：2003-11-06

申请人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

发明人： Wendy Belluomini ,  Ramyanshu Datta ,  Chandler McDowell ,  Robert Montoye ,  Hung Ngo

IPC分类号： G06F7/50 ,  G06F7/60

CPC分类号： G06F7/607

摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

摘要翻译： 一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。 进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。 第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。 由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。 此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。