公开(公告)号：US20070262818A1

公开(公告)日：2007-11-15

申请号：US11707892

申请日：2007-02-02

Applicant: Wen-Chang Lee ,  Ying-Che Tseng

Inventor： Wen-Chang Lee ,  Ying-Che Tseng

IPC: H03G3/30

CPC classification number: H03G7/06 ,  H03G1/0029

Abstract: A variable gain amplifier includes an amplifying circuit and a gain adjusting circuit including the following circuits. A linear exponential transforming circuit transforms a linear controlling signal to output an exponential controlling signal. A voltage buffer circuit is coupled with the linear exponential transforming circuit to receive the exponential controlling signal, outputs a feedback signal to a power transforming circuit, and outputs a voltage controlling signal to control a gain of the amplifying circuit according to the exponential controlling signal and a bias current. A power transforming circuit is coupled with the linear exponential transforming circuit and the voltage buffer circuit to receive the exponential controlling signal and the feedback signal and take two times of a square root of a product of the exponential controlling signal and the feedback signal plus the bias current to output a power signal to the linear exponential transforming circuit.

Abstract translation: 可变增益放大器包括放大电路和包括以下电路的增益调整电路。 线性指数变换电路转换线性控制信号以输出指数控制信号。 电压缓冲电路与线性指数变换电路耦合以接收指数控制信号，将反馈信号输出到功率变换电路，并输出电压控制信号，以根据指数控制信号控制放大电路的增益;以及 偏置电流。 功率变换电路与线性指数变换电路和电压缓冲电路耦合，以接收指数控制信号和反馈信号，并取指数控制信号和反馈信号加上偏置的乘积的平方根的两倍 电流以将功率信号输出到线性指数变换电路。

公开(公告)号：US5920093A

公开(公告)日：1999-07-06

申请号：US834964

申请日：1997-04-07

Applicant: Wen Ling Margaret Huang ,  Ying-Che Tseng

Inventor： Wen Ling Margaret Huang ,  Ying-Che Tseng

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78615 ,  H01L29/78654

Abstract: A semiconductor device (120) is formed in a silicon-on-insulator (SOI) substrate (135). The semiconductor device (120) has a channel region (126) that is controlled by a gate structure (129). The channel region (126) has a doping profile that is essentially uniform where the channel region (126) is under the gate structure (129). This eliminates the parasitic channel region that is common with conventional field effect transistors (FETs) that are formed in SOI substrates. Consequently, the semiconductor device (120) of the present invention does not suffer from the "kink" problem that is common to conventional FET devices.

Abstract translation: 半导体器件（120）形成在绝缘体上硅（SOI）衬底（135）中。 半导体器件（120）具有由栅极结构（129）控制的沟道区（126）。 沟道区（126）具有在沟道区（126）位于栅结构（129）下方的基本上均匀的掺杂分布。 这消除了在SOI衬底中形成的常规场效应晶体管（FET）常见的寄生沟道区。 因此，本发明的半导体器件（120）不会遭受常规FET器件常见的“扭结”问题。