公开(公告)号：US20120119823A1

公开(公告)日：2012-05-17

申请号：US12945543

申请日：2010-11-12

申请人： Hung-Chang Yu

发明人： Hung-Chang Yu

IPC分类号： G05F3/02

CPC分类号： G05F3/242

摘要： A circuit includes a first and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.

摘要翻译： 电路包括第一和第二PMOS晶体管，其中第二PMOS晶体管的栅极耦合到第一PMOS晶体管的栅极和漏极; 第一NMOS晶体管，具有耦合到第一PMOS晶体管的漏极的漏极; 以及第二NMOS晶体管，其中第二NMOS晶体管的漏极耦合到第一NMOS晶体管的栅极，第二NMOS晶体管的栅极和第二PMOS晶体管的漏极。 第一开关耦合在第一PMOS晶体管的漏极和第二PMOS晶体管的漏极之间。 第二开关耦合在第一NMOS晶体管的源极和电接地之间。 第三开关耦合在第二NMOS晶体管的源极和电接地之间。

公开(公告)号：US06717208B2

公开(公告)日：2004-04-06

申请号：US10167123

申请日：2002-06-11

申请人： Hung-Chang Yu ,  Fei-Wen Cheng

发明人： Hung-Chang Yu ,  Fei-Wen Cheng

IPC分类号： H01L29792

CPC分类号： H01L27/11521 ,  H01L27/112 ,  H01L27/1122 ,  H01L27/115

摘要： Disabling flash memory cells to protect their contents, and thus essentially transforming them into read-only memory (ROM) cells, is disclosed. A gate mask and an implant code mask are positioned over a given flash memory cell. A field oxide layer is then fabricated within a substrate layer of the cell through the masks as logically and'ed together. By such fabrication, the flash memory cell is at least partially disabled. The masks are preferably a gate mask and an implant code mask, as these masks typically are already existing and available for use.

摘要翻译： 禁止闪存单元保护其内容，从而基本上将其转换为只读存储器（ROM）单元。 栅极掩模和植入物码掩码位于给定的闪存单元上。 然后通过逻辑上和在一起的掩模，在电池的衬底层内制造场氧化物层。 通过这样的制造，闪存单元至少部分禁用。 掩模优选为栅极掩模和植入物代码掩模，因为这些掩模通常已经存在并且可用于使用。