公开(公告)号：US07606852B2

公开(公告)日：2009-10-20

申请号：US10498707

申请日：2002-12-20

申请人： Koushik Maharatna ,  Eckhard Grass ,  Banerjee Swapna ,  Dhar Anindya Sundar

发明人： Koushik Maharatna ,  Eckhard Grass ,  Banerjee Swapna ,  Dhar Anindya Sundar

IPC分类号： G06F17/16

CPC分类号： G06F7/5446

摘要： A CORDIC unit for the iterative approximation of a vector rotation through a rotary angle θ by a number of elementary rotations through elementary angles αi, including elementary rotation stages for respectively affecting an elementary rotation through an elementary angle αi as an iteration step in the iterative approximation. After such an elementary rotation there remains a residual angle through which rotation is still to be affected. The elementary rotation stages of the CORDIC unit are adapted for rotation through elementary angles αi given by powers of two with a negative integral exponent. The CORDIC unit can also include a triggering device for triggering the elementary rotations, a triggering device which is adapted prior to each iteration step to compare the residual angle to at least one of the elementary angles and to omit those elementary rotation stages whose elementary angles are greater than the residual angle.

摘要翻译： CORDIC单元，用于通过旋转角度θ向量旋转迭代近似通过基本角度α的基本旋转，包括用于分别影响通过基本角度的基本旋转的基本旋转阶段作为迭代近似中的迭代步骤 。 在这样的基本旋转之后，仍然存在一个剩余角度，旋转仍然受到影响。 CORDIC单元的基本旋转级适于通过具有负整数指数的两个功率给出的基本角度alphai进行旋转。 CORDIC单元还可以包括用于触发基本旋转的触发装置，触发装置，其在每个迭代步骤之前被适配以将残余角度与至少一个基本角度进行比较，并且省略基本角度为 大于剩余角度。

公开(公告)号：US07366326B2

公开(公告)日：2008-04-29

申请号：US10875102

申请日：2004-06-24

申请人： Chein-I Chang ,  Jianwei Wang

发明人： Chein-I Chang ,  Jianwei Wang

IPC分类号： G06K9/00

CPC分类号： G06K9/00986 ,  G06F7/5446 ,  G06F17/11 ,  G06K9/0063 ,  G06T7/11 ,  G06T7/194 ,  G06T2200/28 ,  G06T2207/10036 ,  G06T2207/30212

摘要： A Field Programmable Gate Arrays (FPGA) design uses a Coordinate Rotation DIgital Computer (CORDIC) algorithm that can convert a Givens rotation of a vector to a set of shift-add operations. The CORDIC algorithm can be easily implemented in hardware architecture, therefore in FPGA. Since the computation of the inverse of the data correlation matrix involves a series of Givens rotations, the utility of the CORDIC algorithm allows a causal Constrained Energy Minimization (CEM) to perform real-time processing in FPGA. An FPGA implementation of the causal CEM is described and its detailed architecture is also described.

摘要翻译： 现场可编程门阵列（FPGA）设计使用坐标旋转二进制计算机（CORDIC）算法，可将矢量的Givens旋转转换为一组移位加法运算。 CORDIC算法可以在硬件体系结构中轻松实现，因此可以在FPGA中实现。 由于数据相关矩阵的逆的计算涉及一系列Givens旋转，因此CORDIC算法的实用性允许因果约束能量最小化（CEM）在FPGA中执行实时处理。 描述了因果CEM的FPGA实现，并对其详细架构进行了描述。

公开(公告)号：US20070233768A1

公开(公告)日：2007-10-04

申请号：US11712202

申请日：2007-02-28

申请人： Robert Fritsch ,  Romed Schur

发明人： Robert Fritsch ,  Romed Schur

IPC分类号： G06F7/38

CPC分类号： G06F7/4818 ,  G06F7/5446

摘要： The invention relates to continuous computing of an averaged value of a complex signal, in which values are produced by iterative processing, such as CORDIC processing, from digital complex input values of in-phase and quadrature components (si, sq) of the complex signal. The smoothed value is provided by processing the input values by two cascading CORDIC processing units with feedback, and a low-pass filtering contained implicitly therein.

摘要翻译： 本发明涉及复数信号的平均值的连续计算，其中通过诸如CORDIC处理的迭代处理从复数信号的同相和正交分量（si，sq）的数字复输入值产生值 。 通过用反馈进行的两个级联CORDIC处理单元处理输入值，并且其中隐含地包含低通滤波来提供平滑值。

公开(公告)号：US20070214203A1

公开(公告)日：2007-09-13

申请号：US11707618

申请日：2007-02-16

申请人： Hyeong-Seok Yu ,  Jae-Kon Lee ,  Chang-Woo Seo ,  Hyun-Il Kang

发明人： Hyeong-Seok Yu ,  Jae-Kon Lee ,  Chang-Woo Seo ,  Hyun-Il Kang

IPC分类号： G06F17/14

CPC分类号： G06F7/535 ,  G06F7/5446

摘要： A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect to a dividend using the rotation direction for each of the plurality of stages is output.

摘要翻译： 公开了一种使用坐标旋转的分割装置和方法。 为此，顺序执行多个旋转台，直到除数达到标准，并且输出在多个级中的每一个中使用的旋转方向。 输出通过使用针对多个级中的每一个的旋转方向执行关于分红的旋转获得的分割结果。

公开(公告)号：US20030034508A1

公开(公告)日：2003-02-20

申请号：US09930247

申请日：2001-08-16

申请人： MOTOROLA, INC.

发明人： Mihir A. Pandya

IPC分类号： H01L029/76

CPC分类号： G06F7/5446 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. A semiconductor structure formed in accordance with this method includes a monocrystalline silicon substrate, a metal oxide semiconductor portion formed in the monocrystalline silicon substrate, and a compound semiconductor portion formed in the layer of monocrystalline compound semiconductor material. A circuit such as a microprocessor is formed in the complementary metal oxide semiconductor (CMOS) portion, and a coordinate rotation digital computer (CORDIC) functional unit formed in the compound semiconductor portion. The CORDIC algorithms are thus performed in a high speed compound semiconductor structure such as Gallium Arsenide (GaAs) which is integrated with a CMOS microprocessor on a common substrate.

摘要翻译： 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在半导体结构的单晶衬底上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 根据该方法形成的半导体结构包括单晶硅衬底，形成在单晶硅衬底中的金属氧化物半导体部分和形成在单晶化合物半导体材料层中的化合物半导体部分。 在互补金属氧化物半导体（CMOS）部分中形成诸如微处理器的电路，以及形成在化合物半导体部分中的坐标旋转数字计算机（CORDIC）功能单元。 因此，CORDIC算法在诸如砷化镓（GaAs）的高速化合物半导体结构中进行，其在公共衬底上与CMOS微处理器集成。

公开(公告)号：US06480871B1

公开(公告)日：2002-11-12

申请号：US09287281

申请日：1999-04-07

申请人： Dhananjay S. Phatak

发明人： Dhananjay S. Phatak

IPC分类号： G06F7548

CPC分类号： G06F7/5446

摘要： A fast CORDIC algorithm and the resulting VLSI architecture for the evaluation of trigonometric functions are disclosed. The new method employs signed digits to represent intermediate operands and requires a constant scaling or normalization factor which can be pre-computed and made available in read-only hardware for any desired target precision (i.e., word length). The speedup is achieved by performing CORDIC iterations in parallel in two separate modules. Each module executes a “double step” or two basic CORDIC rotations at every iteration cycle. Two angles arctan 2−2i and arctan 2−(2i+1) are used in each step i of the method. As a result, approximately {fraction (n/2)} steps (exactly ⌈ n + 3 2 ⌉ steps) are required to evaluate sine/cosine of n bit input argument up to n bits of accuracy. The VLSI architecture consists of two “zeroing” and two “rotator” modules, each consisting of signed digit adders, latches, shifters, etc. A novel decision block controls the iterations. The new ROM look-up table stores ⌈ n + 3 2 ⌉ values, each accurate to n+3 bits. For every pair of consecutive angles arctan 2−2i and arctan 2−(2i+1) for i=0, 1, 2, . . . , ⌈ n + 3 2 ⌉ only their sum and difference need be stored for the inventive double step branching CORDIC method. The result is a very fast VLSI architecture whose speedup to hardware-overhead ratio is close to 1. The double stepping method can be easily extended to the evaluation of inverse trigonometric, exponential as well as logarithm functions.

摘要翻译： 公开了一种用于评估三角函数的快速CORDIC算法和由此产生的VLSI架构。 新方法使用有符号数字来表示中间操作数，并且需要恒定的缩放或归一化因子，其可以被预先计算并且在只读硬件中可用于任何期望的目标精度（即，字长度）。 通过在两个单独的模块中并行执行CORDIC迭代来实现加速。 每个模块在每个迭代循环中执行“双步”或两个基本的CORDIC旋转。 在该方法的每个步骤i中使用两个角度arctan 2-2i和arctan 2-（2i + 1）。 结果，大概需要n / 2步（精确步骤）来评估n位输入参数的正弦/余弦直到n位的精度。 VLSI架构由两个“归零”和两个“转子”模块组成，每个模块由有符号数字加法器，锁存器，移位器等组成。一个新的判决块控制迭代。 新的ROM查找表存储值，每个精确到n + 3位。 对于i = 0,1,2，...的每对连续角度，对于2-2i和arctan 2-（2i + 1）。 。 。 对于本发明的双步分支CORDIC方法，仅需要存储它们的和差和差。 结果是一个非常快的VLSI架构，其加速到硬件开销比接近1.双步进方法可以很容易地扩展到反三角函数，指数函数和对数函数的评估。

公开(公告)号：US6123671A

公开(公告)日：2000-09-26

申请号：US223950

申请日：1998-12-31

申请人： Steven C. Miller

发明人： Steven C. Miller

IPC分类号： A61B8/00 ,  G01S7/52 ,  G01S7/523 ,  G01S15/89 ,  G06F7/544 ,  G06F7/552 ,  G06T1/00 ,  G10K11/34 ,  H04N7/18 ,  H04R3/00 ,  H04R17/00

CPC分类号： G10K11/346 ,  G01S15/8993 ,  G01S7/52046 ,  G06F7/5446 ,  G06F7/552

摘要： An architecture in which a plurality of delay calculators are distributed throughout the beamformer. Each delay calculator provides beamforming delays and apodization values for a plurality of channels/elements. The delay calculators are initialized with element position coordinates. Then, while imaging, focal coordinates and steering angles are broadcast to all delay calculators. The delay calculator uses a cordic rotator to perform the aperture projections and calculate the hypotenuse. The cordic rotator performs successive coordinate transformations, in two dimensions, using coefficients that are simple powers of two. The resulting apodization values and time delays are then provided by a channel control bus to a plurality of channels.

摘要翻译： 其中多个延迟计算器分布在整个波束形成器中的架构。 每个延迟计算器为多个通道/元件提供波束成形延迟和变迹值。 延迟计算器用元素位置坐标进行初始化。 然后，当成像，焦点坐标和转向角被广播到所有延迟计算器。 延迟计算器使用一个圆心旋转器来执行孔径投影并计算斜边。 绳索旋转器使用两个简单的功率的系数在二维中执行连续的坐标变换。 然后，所产生的变迹值和时间延迟由信道控制总线提供给多个信道。

公开(公告)号：US06055553A

公开(公告)日：2000-04-25

申请号：US28178

申请日：1998-02-23

申请人： Vitit Kantabutra

发明人： Vitit Kantabutra

IPC分类号： G06F7/544 ,  G06F1/02 ,  G06F7/38

CPC分类号： G06F7/5446 ,  G06F2101/04 ,  G06F2101/10

摘要： A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders x.sub.i for every "logical" iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a "physical" iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the y.sub.i 's, which will eventually converge to the desired output.

摘要翻译： 用于计算指数函数的64位精密数字电路和用于计算正弦和余弦的相关64位精密数字电路，每个电路包括主电路和从电路。 主电路使用快速，低精度电路为每个“逻辑”迭代i计算余数+ E，otl x + EE i，从而累积临时错误。 只有在每8个我的结尾，这标志着“物理”迭代的结束，是对所执行的累积错误的完整和快速的校正。 从电路计算称为yi的数量，最终会收敛到期望的输出。

公开(公告)号：US5448747A

公开(公告)日：1995-09-05

申请号：US250122

申请日：1994-05-27

申请人： Steven L. Garverick ,  Kenji Fujino

发明人： Steven L. Garverick ,  Kenji Fujino

IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.

摘要翻译： 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器， 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。

公开(公告)号：US4956799A

公开(公告)日：1990-09-11

申请号：US428035

申请日：1989-10-27

申请人： Takashi Nakayama

发明人： Takashi Nakayama

IPC分类号： G06F7/548 ,  G06F7/544

CPC分类号： G06F7/5446

摘要： A trigonometric function arithmetic processor comprises a first arithmetic unit for executing, in m steps, a pseudo-division operation for obtaining from an initial value .theta. a sequence of numbers {ak} and a pseudoremainder .epsilon. which fulfill the following equation ##EQU1## where a.sub.k =+1 or -1, and the trigonometric function arithmetic processor also comprises a second arithmetic unit for executing the following pseudo-multiplication operation in m steps from initial values Xm=P and Ym=.epsilon..times.P (where P=constant) and the sequence of numbers {a.sub.k }, for k=m-1, m-2, . . . 1 and 0,X.sub.k-1 =X.sub.k -a.sub.k .times.2.sup.-2k .times.Y.sub.kY.sub.k-1 =(Y.sub.k +a.sub.k .times.X.sub.k)/2.sup.kso that X.sub.o =Q.times.cos .theta. nd Yo=Q.times.sin .theta. (Q=constant) are simultaneously obtained.