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21.发明申请公开(公告)号：US20170286063A1
公开(公告)日：2017-10-05
申请号：US15452744
申请日：2017-03-08
发明人： Uri Kaluzhny
摘要： A non-modular multiplier, a method for non-modular multiplication and a computational device are provided. The non-modular multiplier includes an interface and circuitry. The interface is configured to receive n-bit integers A and B. The circuitry is configured to calculate a non-modular product (A*B) by performing a sequence of computations, and to randomize a pattern of an electrical power consumed by the multiplier when performing the sequence. The sequence includes: generating a random number w, determining moduli M1 and M2 that depend on a number R=2k, k equals a bit-length of M1 and M2, and on the random number w, and calculating a first modular product C=A*B % M1 and a second modular product D=A*B % M2, and producing and outputting the non-modular product (A*B) based on the first and second modular products.
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公开(公告)号：US09652200B2
公开(公告)日：2017-05-16
申请号：US14624874
申请日：2015-02-18
申请人： NXP B.V.
发明人： Joppe Bos , Michaël Peeters
CPC分类号： G06F7/4812 , G06F7/723 , G06F7/729 , G06F2207/7261 , H04L9/002 , H04L2209/16
摘要： Various embodiments relate to a method, system, and non-transitory machine-readable medium encoded with instructions for execution by a processor for performing modular exponentiation, the non-transitory machine-readable medium including: instructions for iteratively calculating a modular exponentiation, bd mod n, including: instructions for squaring a working value, c; and instructions for conditionally multiplying the working value, c, by a base value, b, dependent on a bit of an exponent, d, including: instructions for unconditionally multiplying the working value, c, by a lookup table entry associated with the base value.
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公开(公告)号：US20160239267A1
公开(公告)日：2016-08-18
申请号：US14624874
申请日：2015-02-18
申请人： NXP B.V.
发明人： Joppe Bos , Michaël Peeters
IPC分类号： G06F7/48
CPC分类号： G06F7/4812 , G06F7/723 , G06F7/729 , G06F2207/7261 , H04L9/002 , H04L2209/16
摘要： Various embodiments relate to a method, system, and non-transitory machine-readable medium encoded with instructions for execution by a processor for performing modular exponentiation, the non-transitory machine-readable medium including: instructions for iteratively calculating a modular exponentiation, bd mod n, including: instructions for squaring a working value, c; and instructions for conditionally multiplying the working value, c, by a base value, b, dependent on a bit of an exponent, d, including: instructions for unconditionally multiplying the working value, c, by a lookup table entry associated with the base value.
摘要翻译： 各种实施例涉及编码有用于由处理器执行模幂运算的指令的方法，系统和非暂时机器可读介质，所述非暂时机器可读介质包括：用于迭代地计算模幂运算的指令bd mod n，包括：平均工作价值的指示，c; 以及用于有条件地将工作值c乘以基于指数的位d的基本值b的指令，其包括：用于将工作值c无条件乘以与基本值相关联的查找表条目的指令 。
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24.发明授权Residue number system arithmetic operating system, scaling operator, scaling operation method and program and recording medium of the same 失效残差系统算术运算系统，缩放运算符，缩放运算方法以及程序和记录介质公开(公告)号：US08326908B2
公开(公告)日：2012-12-04
申请号：US11340870
申请日：2006-01-27
申请人： Kazuyuki Maruo , Takahiro Yamaguchi
发明人： Kazuyuki Maruo , Takahiro Yamaguchi
IPC分类号： G06F7/38
CPC分类号： G06F7/729
摘要： There is provided a scaling operator for calculating a quotient in a first residue format obtained by dividing an input number in the first residue format by a second modulus in a residue number system for representing numbers by the first residue format of a set of residues obtained with respect to first modulus and residues obtained with respect to second modulus, having a subtracter for outputting inter-moduli values of difference which are values of difference between the residues obtained with respect to the first modulus and the residues obtained with respect to the second modulus and a quotient outputting section for outputting a set of residues of the quotient obtained with respect to the first modulus and residues of the quotient obtained with respect to the second modulus as the quotient based on the inter-moduli values of difference.
摘要翻译： 提供了一种缩放算子，用于计算第一残差格式的商，其通过将第一残差格式中的输入数除以残差数系统中的第二模数，用于表示数字，该第一残差格式是通过以 相对于第二模量获得的第一模量和残余物，具有用于输出差异值的减法器，该减法器是相对于第一模量获得的残差与相对于第二模数获得的残差之间的差的值， 商商输出部分，用于输出相对于第二模数获得的关于第二模数获得的商的残差的一组残差，作为商的差分模值，作为商。
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公开(公告)号：US20110231465A1
公开(公告)日：2011-09-22
申请号：US13044343
申请日：2011-03-09
申请人： Dhananjay S. Phatak
发明人： Dhananjay S. Phatak
IPC分类号： G06F7/72
CPC分类号： G06F7/729
摘要： A method for performing reconstruction using a residue number system includes selecting a set of moduli. A reconstruction coefficient is estimated based on the selected set of moduli. A reconstruction operation is performed using the reconstruction coefficient.
摘要翻译： 使用残差编号系统进行重建的方法包括选择一组模量。 基于所选择的模量集合来估计重建系数。 使用重构系数进行重构动作。
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26.发明授权Modular arithmetic apparatus and method selecting a base in the residue number system 有权模块化算术装置和方法选择残基编号系统中的基数公开(公告)号：US07363335B2
公开(公告)日：2008-04-22
申请号：US11221906
申请日：2005-09-09
申请人： Atsushi Shimbo
发明人： Atsushi Shimbo
IPC分类号： G06F7/38
CPC分类号： G06F7/729
摘要： A modular arithmetic apparatus has a plurality of base parameter sets in read only memories. A base selection unit in the modular arithmetic apparatus selects one of the base parameters sets according to an input modulus p. A plurality of operation units 30, in the modular arithmetic apparatus, perform an arithmetic operation according to the selected base parameter set in parallel and obtain an arithmetic result.
摘要翻译： 模数运算装置在只读存储器中具有多个基本参数集。 模块运算装置中的基本选择单元根据输入模数p选择一个基本参数集。 在该运算装置中，多个运算单元30根据并列设定的基准参数进行算术运算，得到运算结果。
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27.发明授权Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits 失效基于残余数量系统的预计算和双通算法模块化操作方法，在电子集成电路中高效实现加密协议公开(公告)号：US07027598B1
公开(公告)日：2006-04-11
申请号：US09956732
申请日：2001-09-19
CPC分类号： G06F7/728 , G06F7/729 , H04L9/0841 , H04L9/302 , H04L9/3249 , H04L2209/122 , H04L2209/125
摘要： A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.
摘要翻译： 公开了一种在电子集成电路中高效实现加密协议的预计算和双路模块化操作方法。 接收加密的电子消息，并且基于加密协议生成另一个电子消息。 蒙哥马利方法的两遍被用于与加密协议相关联的模块化操作以及基于模数的常数的预计算。 模块化操作可以是模乘法或模幂运算。 可以使用残基数量系统（RNS）和两个RNS碱基之间的转换的两个RNS碱基进行模块化算术。 用于计算的最小数量的寄存器文件以及乘法器电路阵列和模块化还原电路阵列。 所描述的方法允许具有相对较少数量的逻辑门的大型加密密钥的高吞吐量。
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28.发明授权公开(公告)号：US07020674B2
公开(公告)日：2006-03-28
申请号：US10722728
申请日：2003-11-25
申请人： Jordan C. Cookman , Ping Dong
发明人： Jordan C. Cookman , Ping Dong
IPC分类号： G06F7/38
摘要： A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.
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公开(公告)号：US06807555B2
公开(公告)日：2004-10-19
申请号：US10660679
申请日：2003-09-12
申请人： Shinichi Kawamura
发明人： Shinichi Kawamura
IPC分类号： G06F772
摘要： In a modular arithmetic apparatus including a plurality of product-sum circuits having a modular arithmetic function and parallelly arranged, and a correction term calculation unit for calculating a correction term to be used for modular arithmetic operation in the product-sum circuits, the correction term calculation unit sequentially calculates the correction term in units of bits, and each of the product-sum circuits sequentially reflects the correction term calculated by the correction term calculation unit and performs base conversion or base extension.
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30.发明申请公开(公告)号：US20040103134A1
公开(公告)日：2004-05-27
申请号：US10722728
申请日：2003-11-25
申请人： ESS Technology, Inc.
发明人： Jordan C. Cookman , Ping Dong
IPC分类号： G06F007/52
摘要： A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.
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