公开(公告)号：US20120112936A1

公开(公告)日：2012-05-10

申请号：US13189568

申请日：2011-07-25

申请人： Sheng-Jui Huang

发明人： Sheng-Jui Huang

IPC分类号： H03M1/12 ,  H04N7/26

CPC分类号： H03M1/502 ,  H03M3/424

摘要： A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.

摘要翻译： 量化电路包括量化器和补偿电路。 量化器包括电压 - 相位转换器和相位差数字化块。 电压 - 相位转换器被布置用于根据输入电压产生相位信号。 相位差数字化块被配置为根据相位信号的相位和参考相位输入之间的相位差产生量化输出。 补偿电路被配置为根据量化输出对相位差数字化块进行补偿。

公开(公告)号：US20120105694A1

公开(公告)日：2012-05-03

申请号：US13343129

申请日：2012-01-04

申请人： Yoshio Hagihara

发明人： Yoshio Hagihara

IPC分类号： H04N5/335 ,  H03M1/12

CPC分类号： H04N5/378 ,  H03M1/1019 ,  H03M1/502

摘要： Disclosed is a time AD converter which is provided with an annular delay circuit, a digital signal generation unit, and an annular delay circuit control unit. The annular delay circuit has n delay units (where n is a natural number equal to or larger than 2). The digital signal generation unit generates a digital signal corresponding to an analog signal by using an output of the annular delay circuit. The annular delay circuit control unit controls a current which is input to the n delay units in accordance with an external environmental signal.

摘要翻译： 公开了一种设置有环形延迟电路，数字信号生成单元和环形延迟电路控制单元的时间AD转换器。 环形延迟电路具有n个延迟单元（其中n是等于或大于2的自然数）。 数字信号产生单元通过使用环形延迟电路的输出产生与模拟信号相对应的数字信号。 环形延迟电路控制单元根据外部环境信号控制输入到n个延迟单元的电流。

公开(公告)号：US20110292265A1

公开(公告)日：2011-12-01

申请号：US13064910

申请日：2011-04-26

申请人： Tomohiro Takahashi ,  Hiroki Ui ,  Junichi Inutsuka ,  Nozomu Takatori

发明人： Tomohiro Takahashi ,  Hiroki Ui ,  Junichi Inutsuka ,  Nozomu Takatori

IPC分类号： H04N5/335 ,  H03M1/34

CPC分类号： H04N5/378 ,  H03M1/123 ,  H03M1/14 ,  H03M1/502 ,  H03M1/56 ,  H03M1/60 ,  H04N5/3745

摘要： An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.

摘要翻译： 积分A / D转换器包括：比较输入电压与具有斜坡波形的参考电压的比较器，其电压值随时间线性变化; 通过比较器的输出信号的反相触发的高位位计数器启动操作或停止操作，并通过在时钟信号的周期中进行计数来输出高位位; 以及时间 - 数字转换器，其锁存与通过延迟比较器的输出信号而获得的多个信号相对应的时钟信号的相位信息，并对锁存的值进行解码以输出比时钟周期更高的分辨率的低阶位。

公开(公告)号：US20110221621A1

公开(公告)日：2011-09-15

申请号：US13046923

申请日：2011-03-14

申请人： Yasunari Harada

发明人： Yasunari Harada

IPC分类号： H03M1/12

CPC分类号： H03M1/14 ,  H03M1/502

摘要： An A/D conversion circuit includes a pulse transit circuit, first and second pulse transit position detection circuits, and a digital signal generation circuit. The first pulse transit position detection circuit detects a transit position of the pulse signal output from the pulse transit circuit and generates a logical signal according to the transit position. The second pulse transit position detection circuit detects the circling number of the pulse signal output from the pulse transit circuit and generates a logical signal according to the circling number. The digital signal generation circuit synthesizes the logical signals output from the first and second pulse transit position detection circuits and generates a digital signal according to a size of an analog signal VA. The pulse transit circuit is configured so that a sum of the number of the inverting circuits that the pulse signal transits in an N-th period (N denotes a natural number) and the number of the inverting circuits that the pulse signal transits in an (N+1)-th period is a power of 2.

摘要翻译： A / D转换电路包括脉冲传输电路，第一和第二脉冲传输位置检测电路和数字信号发生电路。 第一脉冲通过位置检测电路检测从脉冲传输电路输出的脉冲信号的转接位置，并根据转接位置生成逻辑信号。 第二脉冲通过位置检测电路检测从脉冲传输电路输出的脉冲信号的圈数，并根据圈数生成逻辑信号。 数字信号发生电路合成从第一和第二脉冲通过位置检测电路输出的逻辑信号，并根据模拟信号VA的大小生成数字信号。 脉冲传送电路被配置为使得在第N个周期（N表示自然数）中脉冲信号转换的反相电路的数量和脉冲信号在（ N + 1）个周期是2的幂。

公开(公告)号：US07977980B2

公开(公告)日：2011-07-12

申请号：US12663429

申请日：2008-06-04

申请人： Harald Deppe ,  Holger Flemming

发明人： Harald Deppe ,  Holger Flemming

IPC分类号： H03K5/01

CPC分类号： H03M1/0604 ,  G04F10/10 ,  H03L7/0812 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/06 ,  H03M1/1215 ,  H03M1/502

摘要： A time-to-amplitude component having an integrated designed configured to measure a time difference between a start signal and a stop signal includes a first time-to-amplitude converter having a delay chain, a resistor network, a capacitor configured to be chargeable via the resistor network, and a respective driver. The component further includes a control device and a stabilizing device including a control circuit for generating a regulated control voltage. The first time-to-amplitude converter is configured so that the delay elements of the first time-to-amplitude converter are configured to be controlled by the regulated control voltage, a run signal is transmitted through the delay chain, and the capacitor is continuously charged via the resistor network, and the resistor network is electrically separated from the delay chain via the respective drivers so as to terminate a charging of the capacitor, and the analog voltage signal is measurable at an output of the capacitor.

摘要翻译： 具有集成设计用于测量起始信号和停止信号之间的时间差的集成设计的时间 - 幅度分量包括具有延迟链的第一时间 - 幅度转换器，电阻器网络，经配置以可充电的电容器 电阻网络和相应的驱动器。 该组件还包括控制装置和稳定装置，其包括用于产生调节控制电压的控制电路。 第一时间到幅度转换器被配置为使得第一时间到幅度转换器的延迟元件被配置为由调节的控制电压控制，运行信号通过延迟链传输，并且电容器连续地 通过电阻网络充电，并且电阻网络经由相应的驱动器与延迟链电隔离，以终止电容器的充电，并且模拟电压信号可在电容器的输出端测量。

公开(公告)号：US20110068961A1

公开(公告)日：2011-03-24

申请号：US12955514

申请日：2010-11-29

申请人： Yukie Hashimoto ,  Takamoto Watanabe

发明人： Yukie Hashimoto ,  Takamoto Watanabe

IPC分类号： H03M1/06 ,  H03M1/12

CPC分类号： H03M1/0602 ,  H03M1/0836 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： In a feedback control device (100), a phase compensation unit (13) performs phase compensation in accordance with a phase delay generation in a time A/D conversion circuit (11), which converts an inputted analog signal to digital data, and in a digital signal correction unit (12), which corrects the digital data arbitrarily.

摘要翻译： 在反馈控制装置（100）中，相位补偿单元（13）根据在时间A / D转换电路（11）中的相位延迟生成进行相位补偿，该电路将输入的模拟信号转换为数字数据， 数字信号校正单元（12），任意地校正数字数据。

公开(公告)号：US20100026545A1

公开(公告)日：2010-02-04

申请号：US12446977

申请日：2006-10-25

申请人： Eric Delagnes

发明人： Eric Delagnes

IPC分类号： H03M1/12

CPC分类号： G04F10/005 ,  H03M1/123 ,  H03M1/145 ,  H03M1/502 ,  H03M1/56

摘要： The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . . , 50n) responsive to the output of the comparator and to the clock (102), for interpolating time within a clock period from the triggering time of the comparator, said interpolator delivering a time-interpolation output signal as a fine conversion data which is combined to the coarse conversion data for each conversion cycle. Application to an increased resolution without excess power consumption or increased conversion period.

摘要翻译： 本发明提供了一种单斜波型的模数转换器（ADC），包括斜坡发生器（101），时钟（102），由时钟（102）定时的数字计数器（103），至少 用于数据处理的一个通道（101，...，10i，...，10n），所述或每个通道包括具有连接到斜坡的输入的比较器（201，...，20i，...，20n） 发生器（101），其输出导致每个转换周期将当前计数器值的存储作为粗略的转换数据。 根据本发明，每个信道（101，...，10i，...，10n）还包括延迟链时间内插器（401，...，40i，...，40n， ...，50i，...，50n），响应于比较器和时钟（102）的输出，用于在比较器的触发时间的时钟周期内插入时间，所述内插器递送时间插值输出 信号作为与每个转换周期的粗转换数据组合的精细转换数据。 应用于增加的分辨率，而不需要超出功耗或增加转换周期。

公开(公告)号：US20090021407A1

公开(公告)日：2009-01-22

申请号：US12218531

申请日：2008-07-16

申请人： Tomohito Terazawa ,  Takamoto Watanabe

发明人： Tomohito Terazawa ,  Takamoto Watanabe

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/502

摘要： An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.

摘要翻译： A / D转换器具有一系列M个延迟单元，根据模拟信号的电平，在每个延迟单元中延迟延迟时间，脉冲信号通过该延迟单元被发送。 转换器的单元在N个采样时间中锁存从每个延迟单元输出的脉冲信号，以保持MxN锁存数据。 转换器的另一单元接收M×N个锁存数据作为由按脉冲信号中的M×N个采样点的排列顺序排列的锁存数据组成的一组合数据，将组合数据转换为数字数据 一次延迟到延迟单元中的脉冲信号的位置，并产生对应于来自数字数据的模拟信号电平的转换的数字数据。

公开(公告)号：US20080309542A1

公开(公告)日：2008-12-18

申请号：US12153219

申请日：2008-05-15

申请人： Yukihiko Tanizawa

发明人： Yukihiko Tanizawa

IPC分类号： H03M1/40

CPC分类号： H03M1/089 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： An A/D converter circuit has a first ring delay line and a second ring delay line configured to vary respective characteristics in the same manner relative to a change in the ambient temperature. A reference voltage, which is free from a change in temperature, is fed as a power supply voltage to the second ring delay line. Digital data produced by the first ring delay line is temperature-compensated by digital data produced by the second ring delay line.

摘要翻译： A / D转换器电路具有第一环延迟线和第二环延迟线，其被配置为相对于环境温度的变化以相同的方式改变各自的特性。 没有温度变化的参考电压作为电源电压被馈送到第二环延迟线。 由第一环延迟线产生的数字数据由第二环延迟线产生的数字数据进行温度补偿。

公开(公告)号：US20080204290A1

公开(公告)日：2008-08-28

申请号：US11773330

申请日：2007-07-03

申请人： Amir Parayandeh ,  Aleksandar Prodic

发明人： Amir Parayandeh ,  Aleksandar Prodic

IPC分类号： H03M3/00

CPC分类号： H03K7/08 ,  H02M3/157 ,  H03M1/502

摘要： A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells' propagation times or the effective voltage-to-time conversion ratio in alternative structures.

摘要翻译： 基于电压 - 时间的窗口模数转换器（ADC）可以具有可编程参考电压，转换时间和电压调节精度。 ADC可以在小型硅片上完全实现，适用于高频低功耗开关电源（SMPS）的各种集成数字控制器。 可编程特性可以通过利用延迟线或其他电压 - 时间转换结构的固有平均效应，并通过调整延迟单元的传播时间或有效的电压 - 时间转换比来实现 替代结构。