公开(公告)号：US08464139B2

公开(公告)日：2013-06-11

申请号：US12360477

申请日：2009-01-27

申请人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

发明人： Shunji Miyazaki ,  Kazuhisa Obuchi ,  Norihiro Ikeda

IPC分类号： H03M13/00

CPC分类号： H03M13/2978 ,  H03M13/2975 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： A receiving device in a communication system that separates one frame of information bits into plural blocks, performs turbo encoding of the information bits of each block and transmits the result, and decodes the encoded information bits, where the receiving device includes plural decoders number of which is less than the number of blocks per frame. Each decoder performs a decoding process on encoded information bits of each block that have been expressed by likelihood, when a condition for stopping decoding is met, executes the decoding process of encoded information bits of another block for which decoding has not yet been performed. When the condition for stopping decoding has been met for all blocks before the number of times decoding has been performed for each decoder reaches a preset maximum number of repetitions, the decoding results of all the blocks are serially combined, an error detection process is executed.

摘要翻译： 在将一帧信息比特分离成多个块的通信系统中的接收装置，对每个块的信息比特进行Turbo编码，并发送结果，并对编码的信息比特进行解码，其中接收装置包括多个解码器，其数量为 小于每帧的块数。 当满足停止解码的条件时，每个解码器对已经由似然度表示的每个块的编码信息比特执行解码处理，执行尚未执行解码的另一个块的编码信息比特的解码处理。 在对每个解码器执行解码的次数达到预定的最大重复次数之前，当已经满足所有块的停止解码的条件时，所有块的解码结果被串行组合，执行错误检测处理。

公开(公告)号：US08102923B2

公开(公告)日：2012-01-24

申请号：US11567014

申请日：2006-12-05

申请人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

发明人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

IPC分类号： H04B14/04

CPC分类号： H03M13/2945 ,  H03M13/2903 ,  H03M13/2948 ,  H03M13/2978 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0065 ,  H04L1/007 ,  H04L5/023 ,  H04L2001/0093 ,  H04N21/2381 ,  H04N21/2383 ,  H04N21/2402 ,  H04N21/2404 ,  H04N21/2405 ,  H04N21/6405 ,  H04N21/6408

摘要： Techniques for sending signaling information using hierarchical coding are described. With hierarchical coding, individual messages for users are encoded using multiple interconnected encoders such that (1) the message for each user is sent at a data rate suitable for that user and (2) a single multicast message is generated for the messages for all users. A base station determines data rates supported by the users and the code rates to achieve these data rates. Each data rate is determined by one or more code rates. Signaling information for the users is mapped to data blocks to be sent at different data rates. Each data block is then encoded in accordance with the code rate(s) associated with the data rate for that data block. A final coded block is generated for all users and transmitted. Each user performs the complementary decoding to recover the message sent to that user.

摘要翻译： 描述使用分层编码发送信令信息的技术。 使用分层编码，使用多个互连的编码器对用户的各个消息进行编码，使得（1）以适合于该用户的数据速率发送每个用户的消息，以及（2）为所有用户生成消息的单个多播消息 。 基站确定用户支持的数据速率和码率来实现这些数据速率。 每个数据速率由一个或多个码率决定。 将用户的信令信息映射到以不同数据速率发送的数据块。 然后根据与该数据块的数据速率相关联的码率对每个数据块进行编码。 为所有用户生成最终编码块并进行传输。 每个用户执行补充解码以恢复发送给该用户的消息。

公开(公告)号：US07882416B2

公开(公告)日：2011-02-01

申请号：US11704068

申请日：2007-02-08

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2775 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/6525 ,  H03M13/6561

摘要： General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

摘要翻译： 通用和代数构造的无竞争存储器映射，用于具有所有可能大小的代数交织ARP（几乎规则排列）的并行turbo解码。 提出了一种新颖的手段，其中在执行turbo编码信号的并行解码的上下文中真正地实现了无竞争存储器映射。 提供执行无竞争存储器映射的新颖方式，以确保任何一个turbo解码器（一组并行布置的turbo解码器）在任何给定时间仅访问存储器（一组并行布置的存储器）。 在这样做时，避免turbo解码器和存储器之间的访问冲突。

公开(公告)号：US07571369B2

公开(公告)日：2009-08-04

申请号：US11225479

申请日：2005-09-13

申请人： Yan Wang ,  Eran Pisek ,  Jasmin Oz

发明人： Yan Wang ,  Eran Pisek ,  Jasmin Oz

IPC分类号： H03M13/00

CPC分类号： H03M13/6561 ,  H03M13/2978

摘要： A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples while a second processing unit may be disabled. The number of processing units selected to decode the soft input data samples is determined by a data rate of the received soft input data samples. The reconfigurable turbo decoder also comprises N input data memories that store the received soft input data samples and N extrinsic information memories that store extrinsic information generated by the N processing units. Each of the N processing units is capable of reading from and writing to each of the N input data memories and each of the N extrinsic information memories.

摘要翻译： 一种包括N个处理单元的可重配置turbo解码器。 N个处理单元中的每一个接收软输入数据采样并解码所接收的软输入数据采样。 N个处理单元独立地操作，使得可以选择第一处理单元来解码所接收的软输入数据样本，而可以禁用第二处理单元。 选择用于解码软输入数据样本的处理单元的数量由接收到的软输入数据样本的数据速率确定。 可重新配置的turbo解码器还包括N个输入数据存储器，其存储所接收的软输入数据采样和存储由N个处理单元生成的外在信息的N个非本征信息存储器。 N个处理单元中的每一个能够从N个输入数据存储器和N个非本征信息存储器中的每一个读取和写入。

公开(公告)号：US20080086673A1

公开(公告)日：2008-04-10

申请号：US11704068

申请日：2007-02-08

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2775 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/6525 ,  H03M13/6561

摘要： General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

摘要翻译： 通用和代数构造的无竞争存储器映射，用于具有所有可能大小的代数交织ARP（几乎规则排列）的并行turbo解码。 提出了一种新颖的手段，其中在执行turbo编码信号的并行解码的上下文中真正地实现了无竞争存储器映射。 提供执行无竞争存储器映射的新颖方式，以确保任何一个turbo解码器（一组并行布置的turbo解码器）在任何给定时间仅访问存储器（一组并行布置的存储器）。 在这样做时，避免turbo解码器和存储器之间的访问冲突。

公开(公告)号：US06940928B2

公开(公告)日：2005-09-06

申请号：US09952312

申请日：2001-09-12

申请人： Kelly B. Cameron

发明人： Kelly B. Cameron

IPC分类号： H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  H04L27/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Soft In Soft Out Turbo Code Decoder. Metrics are received by a decoder having SISO unit(s). The SISO unit computes all the alpha values corresponding to a block of data. Of the alpha values computed some alpha values, for example alpha values selected at regular intervals, corresponding to checkpoint values are pushed on a checkpoint stack. Alpha values are computed with some being saved as checkpoint values and some being discarded are computed until the computation reaches a predetermined distance from the end of the block of data. Once the predetermined distance is reached all alpha values are pushed on a computation stack. Once all the values corresponding to the values between the predetermined end of the block and the end of the block have been computed and placed in the computation stack they may be combined with beta values to produce extrinsic values. Once all the values have been used from the computation stack the next checkpoint value can be used to compute another computation stack of alpha values. The alpha values can then be combined with beta values to form extrinsic values and the process continued.

摘要翻译： 软输出Turbo码解码器的方法和装置。 度量由具有SISO单元的解码器接收。 SISO单元计算对应于数据块的所有α值。 计算一些alpha值的Alpha值，例如以定期间隔选择的对应于检查点值的alpha值被推送到检查点堆栈。 计算Alpha值，其中一些被保存为检查点值，并且计算一些被丢弃的值，直到计算达到距数据块结束的预定距离。 一旦达到预定距离，所有的阿尔法值被推送到计算堆栈上。 一旦对应于块的预定端和块结束之间的值的所有值已经被计算并被放置在计算堆栈中，它们可以与β值组合以产生外在值。 一旦从计算堆栈中使用了所有的值，可以使用下一个检查点值来计算alpha值的另一个计算堆栈。 然后可以将α值与β值组合以形成外在值，并且该过程继续。

公开(公告)号：US20050102597A1

公开(公告)日：2005-05-12

申请号：US10926063

申请日：2004-08-26

申请人： Alfonso Martinez ,  Massimo Rovini

发明人： Alfonso Martinez ,  Massimo Rovini

IPC分类号： H03M13/29 ,  H03M13/37 ,  H04L1/00 ,  G06F11/00 ,  H03M13/00

CPC分类号： H04L1/0051 ,  H03M13/2978 ,  H03M13/2987 ,  H03M13/6561 ,  H04L1/0066

摘要： Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PB of a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB≦α·FER*, where FER* is the error rate in the blocks allowed and α

摘要翻译： 迭代解码器包括执行数据块的迭代解码的多个服务器，输入缓冲存储器和执行输入的数据的统计多路复用的控制单元，其首先存储在输入缓冲存储器中并由 其中一个服务器。 输入缓冲存储器包括N + L个存储器位置，其中N是服务器的数量，L是所谓的附加位置的数量。 在所有服务器忙时接收的每个待解码的块被存储在可能可用的L个附加位置中的一个中，或者如果输入缓冲存储器被完全填满则丢失。 附加位置的数量L和服务器的数量N使得根据D / G / N / N + L的排队模型计算出的丢失块的概率P SUB B

公开(公告)号：US20030167432A1

公开(公告)日：2003-09-04

申请号：US10087202

申请日：2002-03-01

申请人： BroadLogic Network Technologies, Inc.

发明人： Wei-Min Zhang ,  Timothy A. Misko

IPC分类号： H04L001/00 ,  G06F011/00

CPC分类号： H03M13/29 ,  H03M13/2978 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0076 ,  H04L25/14

摘要： Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of redundancy data, including the portion of redundancy data in at least one redundancy channel, and transmitting the redundancy channel along with the original channels. Error correction is achieved by receiving at least one redundancy channel and a plurality of original channels, selecting a portion of redundancy data from the redundancy channel, selecting a portion of original data from each of the original channels, and performing at least one decoding operation using the portion of redundancy data and the portions of original data to correct at least one error in the portions of original data.

摘要翻译： 在多信道传输系统中提供了跨多个信道的纠错编码。 具体地，通过从多个原始信道中的每一个选择一部分原始数据来提供冗余，使用原始数据的部分执行至少一个编码操作，以产生冗余数据的至少一部分，包括冗余数据的一部分 至少一个冗余信道，并且与原始信道一起发送冗余信道。 通过接收至少一个冗余信道和多个原始信道，从冗余信道中选择冗余数据的一部分，从每个原始信道中选择一部分原始数据，并使用 冗余数据的部分和原始数据的部分以校正原始数据的部分中的至少一个错误。

公开(公告)号：US20020061070A1

公开(公告)日：2002-05-23

申请号：US09952455

申请日：2001-09-12

发明人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L005/12

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

公开(公告)号：US20020061069A1

公开(公告)日：2002-05-23

申请号：US09952309

申请日：2001-09-12

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L005/12

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*) operation to receive the metrics and a priori values as well as forming min star structures from individual min star operations. Two separate outputs from the min star operation may be maintained separately throughout all calculations and combined only when a final value is required. In addition input to the min star operators that are available prior to a particular decoder iteration may be combined separately to allow an increase in speed within decoding iterations. The same principals apply to the more popular max star operation.

摘要翻译： 用于在地图解码器中执行前向（alpha）和反向（beta）度量的计算的方法和装置。 该方法包括使用最小星号（min *）操作来接收度量和先验值，以及从单个最小星号操作形成最小星型结构。 在所有计算过程中，可以分别维护来自min Star操作的两个独立的输出，并且仅在需要最终值时进行组合。 此外，在特定解码器迭代之前可用的最小星号运算符的输入可以单独组合以允许解码迭代中的速度增加。 相同的原则适用于更受欢迎的最大星号操作。