公开(公告)号：US5760451A

公开(公告)日：1998-06-02

申请号：US803098

申请日：1997-02-20

申请人： Anthony J. Yu

发明人： Anthony J. Yu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/456 ,  Y10S148/019 ,  Y10S148/147 ,  Y10S148/154

摘要： A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide, removing unreacted palladium from the substrate, forming doped silicon on the palladium silicide and substrate, causing the silicon to be transported through the palladium silicide for recrystallizing on the substrate for forming epitaxially recrystallized silicon regions on the substrate and lifting the palladium silicide above the epitaxially recrystallized silicon regions for forming a silicided contact therefor, and removing the doped silicon from the substrate.

摘要翻译： 通过在硅衬底上沉积一层钯，使钯与衬底反应形成钯硅硅化物，从衬底去除未反应的钯，在硅化钯和衬底上形成掺杂硅，从而提供半导体器件的接触，从而引起 通过硅化钯传输的硅用于在衬底上重结晶以在衬底上形成外延再结晶的硅区域，并将外延再结晶的硅区域上的钯硅化物提升，以形成硅化物接触，并从衬底去除掺杂的硅。

公开(公告)号：US5567642A

公开(公告)日：1996-10-22

申请号：US554337

申请日：1995-11-06

申请人： Hyeon S. Kim ,  Choong H. Lee

发明人： Hyeon S. Kim ,  Choong H. Lee

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/28061 ,  H01L21/823842 ,  H01L27/0928 ,  Y10S148/019

摘要： A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.

摘要翻译： 公开了一种制造CMOS器件的栅电极的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层，第一导电层和保护层; 选择性地蚀刻其中将形成PMOS晶体管的保护层的预定部分; 在所述衬底的整个表面上形成第二导电层; 去除形成在保护层上的第二导电层，并将保护层部分蚀刻到预定厚度; 以及使用栅极电极图案来图案化第二导电层，保护层，第一导电层和栅极绝缘层。

公开(公告)号：US5461005A

公开(公告)日：1995-10-24

申请号：US814844

申请日：1991-12-27

申请人： Ajit Manocha ,  Sailesh M. Merchant ,  Ranbir Singh

发明人： Ajit Manocha ,  Sailesh M. Merchant ,  Ranbir Singh

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L21/76889 ,  H01L21/76877 ,  Y10S148/019

摘要： Electrical discontinuities in a silicide formed on a patterned surface are prevented by forming metal fillets in the recesses of the patterned polysilicon covered surface, and then depositing a metal layer and reacting with silicon to form the silicide. The fillet provides extra metal at a place where there is typically a deficiency in conventional deposition techniques.

摘要翻译： 通过在图案化多晶硅被覆表面的凹部中形成金属片，然后沉积金属层并与硅反应以形成硅化物，来防止在图案化表面上形成的硅化物中的电中断。 圆角在常规沉积技术中通常存在缺陷的地方提供额外的金属。

公开(公告)号：US5409853A

公开(公告)日：1995-04-25

申请号：US246532

申请日：1994-05-20

申请人： Anthony J. Yu

发明人： Anthony J. Yu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/66628 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/456 ,  Y10S148/019 ,  Y10S148/147 ,  Y10S148/154

摘要： A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide, removing unreacted palladium from the substrate, forming doped silicon on the palladium silicide and substrate, causing the silicon to be transported through the palladium silicide for recrystallizing on the substrate for forming epitaxially recrystallized silicon regions on the substrate and lifting the palladium silicide above the epitaxially recrystallized silicon regions for forming a silicided contact therefor, and removing the doped silicon from the substrate.

摘要翻译： 通过在硅衬底上沉积一层钯，使钯与衬底反应形成钯硅硅化物，从衬底去除未反应的钯，在硅化钯和衬底上形成掺杂硅，从而提供半导体器件的接触，从而引起 通过硅化钯传输的硅用于在衬底上重结晶以在衬底上形成外延再结晶的硅区域，并将外延再结晶的硅区域上的钯硅化物提升，以形成硅化物接触，并从衬底去除掺杂的硅。

公开(公告)号：US5401674A

公开(公告)日：1995-03-28

申请号：US258330

申请日：1994-06-10

申请人： Mohammed Anjum ,  Ibrahim Burki ,  Craig W. Christian

发明人： Mohammed Anjum ,  Ibrahim Burki ,  Craig W. Christian

IPC分类号： H01L21/285 ,  H01L21/265 ,  H01L21/283

CPC分类号： H01L21/28518 ,  Y10S148/019 ,  Y10S148/032 ,  Y10S148/034 ,  Y10S148/058

摘要： A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.

摘要翻译： 提供了一种减少硅化物生长和生产硅化物所需的温度的方法。 以注入植入物的金属层的中线和下表面以上的浓度峰值密度深度注入锗。 随后的退火导致锗化物占据生长硅化物以上的区域，使得硅原子的消耗减少，并且将硅化物形成为受控的厚度。

公开(公告)号：US5391520A

公开(公告)日：1995-02-21

申请号：US139268

申请日：1993-10-18

申请人： Fusen Chen ,  Fu-Tai Liou ,  Girish Dixit

发明人： Fusen Chen ,  Fu-Tai Liou ,  Girish Dixit

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L23/53257 ,  H01L21/76889 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S257/915

摘要： A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed. The refractory metal layer and barrier layer, and the refractory metal silicide layer if formed, are etched to define a conductive interconnect between the exposed selected regions of the first and second conductive structures.

摘要翻译： 公开了一种用于制造集成电路中的局部互连的方法，以及根据该集成电路形成的集成电路。 根据所公开的实施例，在集成电路上形成第一和第二导电结构。 在整合上形成绝缘层。 第一光致抗蚀剂层形成在绝缘层上，被图案化和显影。 蚀刻绝缘层以暴露第一和第二导电结构的选定区域。 在集成电路上形成难熔金属层。 在耐火金属层之上形成阻挡层，并且可选地在阻挡层上形成难熔金属硅化物层。 第二光致抗蚀剂层形成在阻挡层上，被图案化和显影。 难熔金属层和阻挡层以及如果形成的难熔金属硅化物层被蚀刻以在第一和第二导电结构的暴露的选定区域之间限定导电互连。

公开(公告)号：US5344793A

公开(公告)日：1994-09-06

申请号：US26944

申请日：1993-03-05

申请人： Heinrich Zeininger ,  Christoph Zeller ,  Udo Schwalke ,  Uwe Doebler ,  Wilfried Haensch

发明人： Heinrich Zeininger ,  Christoph Zeller ,  Udo Schwalke ,  Uwe Doebler ,  Wilfried Haensch

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L29/456 ,  H01L21/28518 ,  H01L2924/0002 ,  Y10S148/017 ,  Y10S148/019 ,  Y10S438/974

摘要： An method of providing defect enhanced CoSi2 formation and improved silicided junctions in deep submicron MOSFETs. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.

摘要翻译： 在深亚微米MOSFET中提供缺陷增强的CoSi2形成和改进的硅化物结的方法。 具有扩散窗的硅晶片首先用氢氟酸预清洗。 在HF预清洗之后，将硅晶片转移到常规的钴溅射工具，其中通过用低能Ar +离子轰击进行溅射清洗，以形成超浅损伤区域。 在溅射清洗之后，并且不从溅射工具移除晶片，在室温下将钴金属沉积在硅晶片上，并且在扩散窗中形成CoSi 2层。

公开(公告)号：US5322809A

公开(公告)日：1994-06-21

申请号：US60774

申请日：1993-05-11

申请人： Mehrdad Moslehi

发明人： Mehrdad Moslehi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/66545 ,  Y10S148/019 ,  Y10S148/147

摘要： A self-aligned silicide process that enables different silicide thicknesses for polysilicon gates and source/drain junction regions. Semiconductor body (10) includes a doped well (14) formed in substrate (12). Field insulating region (18) is located above channel stop region (16) in doped well (14). Implanted within doped well (14) are source/drain junctions (34). Source/drain junctions (34) are shallow heavily doped regions. The surfaces of source/drain junctions (34) are silicided. Silicide gate (44) is separated from the surface of doped well (14) by gate insulator layer (20) and contains a silicide layer (40) and a doped polysilicon layer (22). The thickness of silicide layer (40) is not limited by the thickness of the silicided surfaces of source/drain junctions (34) or the amount of silicon consumed over these junctions. Silicon nitride sidewall spacers (32) separate the sidewall edges of silicide gate (44) and the transistor channel region from the source/drain junction silicide layer 41.

摘要翻译： 自对准硅化物工艺，其能够实现多晶硅栅极和源极/漏极结区域的不同硅化物厚度。 半导体本体（10）包括形成在衬底（12）中的掺杂阱（14）。 场绝缘区域（18）位于掺杂阱（14）中的通道停止区域（16）的上方。 掺杂在掺杂阱（14）内的是源极/漏极结（34）。 源极/漏极结（34）是浅重掺杂区域。 源极/漏极结（34）的表面被硅化。 硅化物栅极（44）通过栅极绝缘体层（20）与掺杂阱（14）的表面分离，并且包含硅化物层（40）和掺杂多晶硅层（22）。 硅化物层（40）的厚度不受源极/漏极结（34）的硅化物表面的厚度或在这些结上消耗的硅的量的限制。 氮化硅侧壁间隔件（32）将硅化物栅极（44）的侧壁边缘和晶体管沟道区域与源极/漏极结硅化物层41分离。

公开(公告)号：US5302552A

公开(公告)日：1994-04-12

申请号：US38045

申请日：1993-03-26

申请人： Johan P. W. B. Duchateau ,  Alec H. Reader ,  Gerrit J. Van Der Kolk

发明人： Johan P. W. B. Duchateau ,  Alec H. Reader ,  Gerrit J. Van Der Kolk

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76889 ,  H01L29/665 ,  H01L29/7848 ,  Y10S148/019 ,  Y10S148/147 ,  Y10S438/934

摘要： A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semiconductor body (1) is heated during a heat treatment to a temperature at which the Co or Ni forms a metal silicide with the silicon (3, 4, 5, 6), but not with the insulating material (8, 9). On the surface (2) of the layer (12) containing the Co or Ni, according to the invention, a layer of an amorphous alloy of this metal with a metal from a group comprising Ti, Zr, Ta, Mo, Nb, Hf and W is deposited, while furthermore the temperature is so adjusted during the heat treatment that the layer (12) of the amorphous alloy remains amorphous during the heat treatment. In this way a metal silicide is formed on the silicon regions (3, 4, 5, 6) only and not on the regions of insulating material ( 8, 9) directly adjoining them; in other words, the method yields a self-aligned metal silicide.

摘要翻译： 一种制造半导体器件的方法，其中包含Co或Ni的层（12）沉积在由硅区域（3,4,5,6）限定的半导体本体（1）的表面（2）和绝缘材料区域 （8,9），之后半导体本体（1）在热处理期间被加热到Co或Ni与硅（3,4,5,6）形成金属硅化物的温度，但不与 绝缘材料（8,9）。 在根据本发明的包含Co或Ni的层（12）的表面（2）上，该金属与由Ti，Zr，Ta，Mo，Nb，Hf组成的组中的金属的非晶合金层 并且沉积W，同时在热处理期间温度如此调节，使得非晶合金层（12）在热处理期间保持无定形。 以这种方式，在硅区域（3,4,5,6）上形成金属硅化物，而不是直接与它们相邻的绝缘材料（8,9）的区域上形成金属硅化物; 换句话说，该方法产生自对准的金属硅化物。

公开(公告)号：US5279887A

公开(公告)日：1994-01-18

申请号：US843818

申请日：1992-02-28

申请人： James Brady ,  Tsiu C. Chan ,  David S. Culver

发明人： James Brady ,  Tsiu C. Chan ,  David S. Culver

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L23/53271 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

摘要翻译： 接触结构提供两个多晶硅互连层之间的电接触。 下层在其上表面具有硅化物层。 上部多晶硅层可以掺杂不同的导电类型，并与下部多晶硅层的硅化物区域欧姆接触。