公开(公告)号：US20150325553A1

公开(公告)日：2015-11-12

申请号：US14804249

申请日：2015-07-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DongSam Park ,  YongDuk Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/05552 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Abstract translation: 半导体器件具有在衬底的表面上具有第一导电层的衬底和暴露第一导电层的多个空腔。 具有导电TSV的第一半导体管芯被安装到基板的空腔中。 第一绝缘层形成在衬底和第一半导体管芯上并延伸到空腔中以将第一半导体管芯嵌入衬底内。 去除第一绝缘层的一部分以暴露导电TSV。 在导电TSV上形成第二导电层。 去除第一导电层的一部分以形成第一导电层的电通常或电隔离的导电段。 第二绝缘层形成在衬底和第一导电层的导电段上。 第二半导体管芯安装在电连接到第二导电层上的衬底上。

公开(公告)号：US09177930B2

公开(公告)日：2015-11-03

申请号：US13621810

申请日：2012-09-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Abstract translation: 倒装芯片半导体封装具有带有多个有源器件的衬底。 接触焊盘形成在与多个有源器件电接触的衬底上。 在基板和中间导电层之间形成钝化层，第二阻挡层和粘附层。 中间导电层与接触垫电接触。 通过在中间导电层上电镀形成铜内核柱。 内芯柱具有矩形，圆柱形，环形或中空圆柱形。 通过电镀焊料材料并回流焊料材料形成焊料凸点，在内芯柱周围形成焊料凸块。 在内芯柱和焊料凸块之间形成第一阻挡层和润湿层。 焊料凸块与中间导电层电接触。

公开(公告)号：US09177832B2

公开(公告)日：2015-11-03

申请号：US13234535

申请日：2011-09-16

Applicant: Zigmund R. Camacho

Inventor： Zigmund R. Camacho

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.

Abstract translation: 半导体器件具有带有半导体管芯安装区域的载体。 多个导电柱形成在半导体管芯安装区域的周边和载体中。 移除载体的第一部分以暴露多个导电柱的第一部分，使得多个导电柱的第二部分嵌入载体的第二部分中。 第一半导体管芯安装到半导体管芯安装区域和多个导电柱的第一部分之间。 围绕第一半导体管芯并围绕多个导电柱的第一部分沉积第一密封剂。 移除载体的第二部分以暴露多个导电柱的第二部分。 在多个导电柱和第一半导体管芯之上形成互连结构。

公开(公告)号：US20150311172A1

公开(公告)日：2015-10-29

申请号：US14745056

申请日：2015-06-19

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13109 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的多个复合凸块的半导体管芯。 复合凸块具有可熔部分和不可熔部分，例如形成在导电柱上的导电柱和凸块。 复合凸块也可以是锥形的。 导电迹线形成在具有从平面图平行于导电迹线的边缘的互连位置的衬底上，以增加逃逸路由密度。 互连部位可以具有小于导电迹线宽度的1.2倍的宽度。 复合凸块比互连部位宽。 复合凸块的可熔部分结合到互连部位，使得可熔部分覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的复合凸块沉积密封剂。

公开(公告)号：US09171795B2

公开(公告)日：2015-10-27

申请号：US14556992

申请日：2014-12-01

Applicant: Dong Ju Jeon ,  KyoungHee Park ,  YoungDal Roh ,  JinHee Jung

Inventor： Dong Ju Jeon ,  KyoungHee Park ,  YoungDal Roh ,  JinHee Jung

IPC: H01L21/4763 ,  H01L23/04 ,  H05K1/18 ,  H01L23/498 ,  H01L21/52 ,  H01L21/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/49861 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4821 ,  H01L21/486 ,  H01L21/52 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.

Abstract translation: 一种集成电路封装系统及其集成电路封装系统的制造方法，包括：嵌入材料在部件上; 嵌入材料上的掩模层; 掩模图案中的掩埋图案，掩模图案的外表面与掩模层的外表面共面，埋入图案电连接到部件; 在掩埋图案的一部分上的图案化电介质; 并在埋藏图案上集成电路裸片。

公开(公告)号：US09171739B1

公开(公告)日：2015-10-27

申请号：US14313452

申请日：2014-06-24

Applicant: YoungDal Roh ,  DeokKyung Yang ,  HeeSoo Lee

Inventor： YoungDal Roh ,  DeokKyung Yang ,  HeeSoo Lee

IPC: H01L23/28 ,  H01L21/44 ,  H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/14 ,  H01L2924/15311

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：图案化的第一导电电镀; 在图案化的第一导电电镀上的模制品; 通过成型的通孔; 在模制件和通孔上的第二导电电镀; 部分地覆盖第一导电镀层，第二导电镀层和模制件的保护层; 第一导电电镀装置; 以及连接到第二导电电镀层的外部连接器。

公开(公告)号：US09147662B1

公开(公告)日：2015-09-29

申请号：US14137755

申请日：2013-12-20

Applicant: Byung Tai Do ,  Arnel Senosa Trasporto ,  Sung Soo Kim

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Sung Soo Kim

IPC: H01L23/492 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit packaging system including: a fiber-less organic substrate including: a first dielectric layer, a first metal layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and the first metal layer, and an interconnect via plated on the first metal layer and the second dielectric layer; an integrated circuit mounted over the second dielectric layer; and an integrated circuit interconnect between the integrated circuit and the interconnect via.

Abstract translation: 一种集成电路封装系统，包括：无纤维有机基底，包括：第一介电层，第一介电层上的第一金属层，第一介电层和第一金属层上的第二介电层，以及经电镀的互连 在第一金属层和第二介电层上; 安装在所述第二电介质层上的集成电路; 以及集成电路和互连通孔之间的集成电路互连。

公开(公告)号：US09142515B2

公开(公告)日：2015-09-22

申请号：US14087653

申请日：2013-11-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  DaeSik Choi ,  Jun Mo Koo

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/34 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/19 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract translation: 半导体晶片具有多个第一半导体管芯。 第二半导体管芯安装到第一半导体管芯。 在第一和第二半导体管芯之间形成屏蔽层。 在第一和第二半导体管芯之间形成诸如导电柱，凸起或接合线的电互连。 可以通过第一和第二半导体管芯形成导电TSV。 密封剂沉积在第一和第二半导体管芯和电互连上。 在第二半导体管芯上形成散热器。 可以在第二半导体管芯上形成诸如凸块的互连结构。 去除第一半导体管芯的背面的一部分。 在第一半导体管芯的暴露表面上形成保护层。 保护层覆盖第一半导体管芯的暴露的背面和侧壁。

公开(公告)号：US20150262977A1

公开(公告)日：2015-09-17

申请号：US14728182

申请日：2015-06-02

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Abstract translation: 半导体器件具有第一互连结构。 第一半导体管芯具有朝向并安装到第一互连结构的第一表面的有源表面。 第一密封剂沉积在第一互连结构和第一半导体管芯上。 第二半导体管芯具有朝向并安装到与第一表面相对的第一互连结构的第二表面的有源表面。 多个第一导电柱形成在第一互连结构的第二表面上并且围绕第二半导体管芯。 第二密封剂沉积在第二半导体管芯上并围绕多个第一导电柱。 包括导电层和凸块的第二互连结构形成在第二密封剂上并且电连接到多个第一导电柱和第一和第二半导体管芯。

公开(公告)号：US09129978B1

公开(公告)日：2015-09-08

申请号：US14313521

申请日：2014-06-24

Applicant: Jaepil Kim ,  Seokhyun Kim ,  Daeup Bae ,  Jaewon Kim ,  Jaekang Yoo ,  Sungpil Hur

Inventor： Jaepil Kim ,  Seokhyun Kim ,  Daeup Bae ,  Jaewon Kim ,  Jaekang Yoo ,  Sungpil Hur

IPC: H01L23/48 ,  H01L23/28 ,  H01L21/44 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, includes: a singulation substrate having an air vent portion having longitudinal grooves in the air vent portion, the longitudinal grooves all parallel to each other; an integrated circuit die attached to the singulation substrate; and a molding compound on the singulation substrate, on the air vent portion, in a portion of the longitudinal grooves, and on the integrated circuit die.

Abstract translation: 一种集成电路封装系统及其集成电路封装系统的制造方法，其特征在于，包括：排气基板，其具有在所述排气部中具有纵向槽的排气部，所述纵向槽全部平行; 附接到单片基板的集成电路芯片; 在分离基板上，排气部分，纵向槽的一部分和集成电路管芯上的模塑料。