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公开(公告)号：US07742352B1
公开(公告)日：2010-06-22
申请号：US11927845
申请日：2007-10-30
IPC分类号： G11C7/02
CPC分类号： G11C17/18 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/027 , G11C29/12005 , G11C29/48 , G11C29/50008
摘要： Techniques for use with a fuse-based non-volatile memory circuit include digitally controlling a resistance threshold of the circuit. The circuit includes a fuse circuit and a comparator circuit. The comparator circuit is configured to compare a first signal indicative of the fuse resistance to a second signal indicative of a reference level. At least one of the first and second signals is digitally controllable. The comparator circuit is configured to generate a digital output signal indicative of the comparison. The circuit may include a first digital-to-analog converter circuit configured to generate a first analog signal based on at least a first plurality of digital signals. The first signal is at least partially based on the first analog signal. The circuit may include a control circuit configured to digitally control the digitally controllable ones of the first and second signals at least partially based on the digital output signal.
摘要翻译： 与基于熔丝的非易失性存储器电路一起使用的技术包括数字地控制电路的电阻阈值。 电路包括熔丝电路和比较器电路。 比较器电路被配置为将指示熔丝电阻的第一信号与指示参考电平的第二信号进行比较。 第一和第二信号中的至少一个是数字可控的。 比较器电路被配置为产生指示比较的数字输出信号。 电路可以包括被配置为基于至少第一多个数字信号产生第一模拟信号的第一数模转换器电路。 第一信号至少部分地基于第一模拟信号。 电路可以包括控制电路，其被配置为至少部分地基于数字输出信号数字地控制第一和第二信号中的数字可控的信号。
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公开(公告)号：US07738421B2
公开(公告)日：2010-06-15
申请号：US12196592
申请日：2008-08-22
IPC分类号： H04W4/00
摘要： A system provides push services and information to mobile stations via broadcast messages. The broadcast messages are made on predetermined cell broadcast channels, which are associated with an inbox on the mobile stations. Contained within the messages are Uniform Resource Locators (URL) that, when accessed, provide multimedia and other rich content to the mobile station. The system allows wireless carriers to provide features such as Wireless Access Protocol (WAP) push operations via cell broadcast to many mobile stations in a geographic area without the need to individually address messages to the mobile stations.
摘要翻译： 系统通过广播消息向移动台提供推送服务和信息。 广播消息是在与移动台上的收件箱相关联的预定小区广播信道上进行的。 在消息中包含统一资源定位符（URL），当被访问时，向移动台提供多媒体和其他丰富的内容。 该系统允许无线运营商通过小区广播提供诸如无线接入协议（WAP）推送操作的功能到地理区域中的许多移动台，而不需要单独地向移动台寻址消息。
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公开(公告)号：US07671688B2
公开(公告)日：2010-03-02
申请号：US12032407
申请日：2008-02-15
申请人： Augusto Marques
发明人： Augusto Marques
摘要： A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.
摘要翻译： 可编程的无参考振荡器提供了广泛的可编程输出频率。 可编程基准无源振荡器在集成电路上实现，该集成电路包括自由运行的可控振荡器电路，例如压控振荡器（VCO），可编程分频器电路，其被耦合以根据可编程分频值对可控振荡器电路的输出进行分频 。 非易失性存储器存储编程的分频值和控制可控振荡器电路的输出的控制字。 控制字提供校准功能，以结合可编程分频器电路实现所需的输出频率。 通过根据由集成电路上的温度传感器检测到的温度调节控制字来实现开环温度补偿。 可以通过调整过程控制字和温度来实现额外的时钟精度。
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公开(公告)号：US07642873B2
公开(公告)日：2010-01-05
申请号：US11695009
申请日：2007-03-31
申请人： Steven T. Sprouse
发明人： Steven T. Sprouse
CPC分类号： H03L3/00 , Y10T29/4913
摘要： An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.
摘要翻译： 振荡器电路可以与被设计为与晶体一起操作的控制器电路一起使用，而不改变控制器电路的引脚分布或固件。 在一些实施例中，振荡器电路包括响应于低振幅跃迁的使能输入，其可耦合到控制器电路的晶体输出信号并由其驱动。 当晶体输出信号上存在转换时，振荡器电路使能其时钟输出信号。 当控制器电路禁止其晶体输出信号时，振荡器电路不再检测耦合到振荡器电路使能输入的晶体输出信号的转换，并禁用时钟输出信号。
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公开(公告)号：US07629654B2
公开(公告)日：2009-12-08
申请号：US11949654
申请日：2007-12-03
申请人： Wesley H. Morris
发明人： Wesley H. Morris
CPC分类号： H01L29/66477 , H01L21/761 , H01L23/552 , H01L27/0921 , H01L29/1083 , H01L29/1087 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
摘要翻译： 半导体器件可以使用常规设计和工艺制造，但包括专门的结构以减少或消除由各种形式的辐射引起的有害影响。 这样的半导体器件可以包括在本申请中公开的一个或多个寄生隔离器件和/或掩埋保护环结构。 适应这些新颖结构的设计和/或工艺步骤的引入与常规CMOS制造工艺兼容，因此可以以相对低的成本和相对简单的方式实现。
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36.发明授权公开(公告)号：US07558579B2
公开(公告)日：2009-07-07
申请号：US11155585
申请日：2005-06-20
IPC分类号： H04Q7/00
CPC分类号： H04W76/10 , H04W76/12 , H04W76/30 , H04W92/02 , H04W92/045
摘要： A system and a method for connecting a call through a telecommunications network. A base station, connected to a public switched telephone network, includes a call processor, a memory and a transceiver. The memory includes a database containing dialing instructions for a wireless station for a telephone connection through the public switched telephone network to a destination station. The transceiver receives a call request from the wireless station, and the call processor in response to the call request, accesses the database and dials a call for connection through the public switched telephone network to the destination station based on the dialing instructions for the wireless station.
摘要翻译： 一种通过电信网络连接呼叫的系统和方法。 连接到公共交换电话网络的基站包括呼叫处理器，存储器和收发器。 存储器包括数据库，该数据库包含用于通过公共交换电话网络到目的地站的电话连接的无线站的拨号指令。 收发器从无线站接收呼叫请求，呼叫处理器响应于呼叫请求，基于无线站的拨号指令访问数据库并通过公共交换电话网拨打到连接目的地的呼叫 。
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37.发明授权Passive element memory array incorporating reversible polarity word line and bit line decoders 有权无源元件存储阵列，包含可逆极性字线和位线解码器公开(公告)号：US07554832B2
公开(公告)日：2009-06-30
申请号：US11461339
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US07551009B2
公开(公告)日：2009-06-23
申请号：US11680016
申请日：2007-02-28
CPC分类号： H03K23/54 , H03K19/0016
摘要： A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off.
摘要翻译： 一种用于将具有第一频率的信号除以分频比的方法包括基于分频比选择具有第二频率的至少一个信号的第一脉冲宽度，并且通过至少一个多个脉冲中的相应一个产生 响应于具有第二脉冲宽度的至少一个信号的宽度控制电路。 所述方法包括选择所述多个脉冲宽度控制电路中的至少一个被加电以产生所述至少一个信号。 多个脉冲宽度控制电路中的至少一个包括第一脉冲宽度控制电路，用于产生具有第一脉冲宽度，第二频率和第一相位的第一信号。 第一信号对应于具有第一相位的选择电路输出信号。 该方法包括选择要断电的多个脉冲宽度控制电路中的至少一个。
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公开(公告)号：US07548123B2
公开(公告)日：2009-06-16
申请号：US11777779
申请日：2007-07-13
申请人： Douglas R. Frey
发明人： Douglas R. Frey
CPC分类号： H03L7/0802 , H03L7/085 , H03L7/087 , H03L7/0891 , H03L7/10 , H03L7/1976
摘要： A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.
摘要翻译： 锁相环（PLL）使用驱动二进制相位检测器的路线分数N分频器来实现初始锁定。 一旦达到频率锁定，该分频器可能会关闭，而自适应相位检测器接管PLL前端的控制。 自适应相位检测器（APD）直接从VCO和参考时钟接收输入，导出数字控制信号和精密相位检测器输出。 APD以更新速率工作，产生以更新速率输出的数字Δ-Σ调制器（DSM）数据流。 APD自动锁定到与VCO输出和参考时钟之间的期望差异相对应的数字产生的斜坡，同时自适应地校正DC误差和斜坡消除误差。
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公开(公告)号：US07542370B2
公开(公告)日：2009-06-02
申请号：US11618844
申请日：2006-12-31
申请人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
发明人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C2213/31 , G11C2213/32 , G11C2213/35
摘要： A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.
摘要翻译： 公开了一种可逆极性解码器电路，其特别适用于实现多头解码器结构，例如可用于解码字线，特别是在3D存储器阵列中。 解码器电路向半选择的字线驱动电路的栅极提供过驱动电压偏置，以将半选择的字线牢固地保持在非活动电平。 如果存储器阵列被偏置在或接近击穿电压，则该过驱动电压可能大于解码晶体管的击穿电压。 然而，在所描述的实施例中，解码器电路实现这一点，而不会对解码器电路的任一极性进行施加大于任何解码晶体管的击穿电压的电压。
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