公开(公告)号：US06864148B1

公开(公告)日：2005-03-08

申请号：US10655705

申请日：2003-09-05

申请人： Chia-Shun Hsiao ,  Dong Jun Kim

发明人： Chia-Shun Hsiao ,  Dong Jun Kim

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/76 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/823481 ,  H01L29/42368

摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

公开(公告)号：US06730565B2

公开(公告)日：2004-05-04

申请号：US10277848

申请日：2002-10-22

申请人： Min-Soo Cho ,  Dong-Jun Kim ,  Jin-Woo Kim

发明人： Min-Soo Cho ,  Dong-Jun Kim ,  Jin-Woo Kim

IPC分类号： H10L21336

CPC分类号： H01L27/11519 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.

摘要翻译： 本发明提供一种形成分离式闪存的方法。 在氮化硅层之间的浮栅层暴露之后，在氮化硅层图案的侧壁上形成导电层间隔物。 导电层隔离物形成在随后完成的闪速存储器的浮动栅极中，以形成在擦除操作中将隧道集中在其上的尖端。 也就是说，间隔物形成在浮动栅极层上的氮化硅层图案的侧壁上以形成隧道末端。

公开(公告)号：US06326259B1

公开(公告)日：2001-12-04

申请号：US09852602

申请日：2001-05-10

申请人： Kyong Min Kim ,  Han Sang Song ,  Dong Jun Kim

发明人： Kyong Min Kim ,  Han Sang Song ,  Dong Jun Kim

IPC分类号： H01L218242

CPC分类号： H01L28/56 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/31604 ,  H01L28/91

摘要： A method of manufacturing a capacitor in a semiconductor device uses a metal as an upper electrode and a lower electrode, and forms a dielectric film in a double structure of a titanium-containing tantalum oxide film and an amorphous tantalum oxide film. Therefore, the invention can secure a sufficient capacitance while improving an electrical characteristic of the capacitor.

摘要翻译： 在半导体器件中制造电容器的方法使用金属作为上部电极和下部电极，并且在含钛的钽氧化物膜和非晶形氧化钽膜的双重结构中形成电介质膜。 因此，本发明可以确保足够的电容，同时改善电容器的电特性。

公开(公告)号：US6091116A

公开(公告)日：2000-07-18

申请号：US443283

申请日：1995-05-17

申请人： Dong-jun Kim ,  Jeong-hyuk Choi

发明人： Dong-jun Kim ,  Jeong-hyuk Choi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823892 ,  H01L27/0922

摘要： A CMOS device includes first and second wells formed in first and second regions of a semiconductor substrate, respectively. First and second transistors are formed in the respective wells. A third transistor is formed in a third region of the semiconductor substrate outside of the wells. A first impurity layer is formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer, deeper than the first impurity layer, is formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without requiring any additional, separate mask processing steps.

摘要翻译： CMOS器件分别包括在半导体衬底的第一和第二区域中形成的第一阱和第二阱。 第一和第二晶体管形成在相应的阱中。 在阱的外部的半导体衬底的第三区域中形成第三晶体管。 在第一，第二和第三区域中的至少一个但不多于两个的耗尽区附近形成第一杂质层，并且在该区域中形成比第一杂质层更深的第二杂质层 其中不形成第一杂质层的衬底的一个或多个。 一种用于制造这种CMOS器件的方法使得第一，第二和第三晶体管的穿通电压特性能够最佳地不同，而不需要任何额外的分开的掩模处理步骤。

公开(公告)号：US5936887A

公开(公告)日：1999-08-10

申请号：US910025

申请日：1997-08-12

申请人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

发明人： Jung-Dal Choi ,  Dong-Jun Kim ,  Wang-Chul Shin ,  Jong-Han Kim

IPC分类号： H01L21/8247 ,  G11C11/56 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C11/5621 ,  G11C16/0483 ,  H01L27/11521 ,  G11C16/24 ,  G11C2211/5649 ,  G11C7/18

摘要： A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12. The memory device also comprises a string selector for selecting either the first string 11a or the second string 11b in response to signals from string select lines SSL1 and SSL2, and a plurality of plate lines PLa or 21a and PLb or 21b which are respectively arranged on the first and second strings 11a and 11b. In the memory cell, if voltages having different levels are applied to the control gate of a memory cell of the string selected thus and the plate line, at least more than two coupling voltages are induced to a floating gate of a corresponding memory cell so that two bits of information can be stored in and read out of one memory cell. The memory device has a cell structure in which a pair of two adjacent memory cell strings are commonly connected to one bit line, so that margin width between two bit lines, i.e., a bit line pitch can be relatively widely obtained.

摘要翻译： 公开了一种非易失性存储器件，其中一对两个相邻的存储器单元串共同连接到一个位线，并且存储器单元串被选择性地驱动以在两个位线之间获得相对较宽的间距余量。 该装置具有沿着每个存储单元串或一对存储单元串定位的导电板线，以将具有相对低的编程电压的存储单元驱动到字线。 存储器件包括彼此并联布置的多个存储单元串，并且每个存储单元串沿与位线12相同的方向延伸，并且一对两个相邻的存储单元串11a和11b共同连接到 存储装置还包括用于响应于来自串选择线SSL1和SSL2的信号以及多个板线PLa或21a和PLb或21b而选择第一串11a或第二串11b的串选择器，其中 分别布置在第一和第二弦11a和11b上。 在存储单元中，如果将具有不同电平的电压施加到由此选择的串的存储单元的控制栅极和板线，则至少两个耦合电压被感应到相应存储单元的浮动栅极，使得 两位信息可以存储在一个存储单元中并从其中读出。 存储器件具有单元结构，其中一对两个相邻的存储单元串共同连接到一个位线，使得可以相对广泛地获得两个位线之间的裕度宽度，即位线间距。

公开(公告)号：US5734609A

公开(公告)日：1998-03-31

申请号：US757266

申请日：1996-11-29

申请人： Jung-dal Choi ,  Dong-Jun Kim

发明人： Jung-dal Choi ,  Dong-Jun Kim

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0483

摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.

摘要翻译： 具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列， 。 这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和 擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以 分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。

公开(公告)号：US5729491A

公开(公告)日：1998-03-17

申请号：US745731

申请日：1996-11-12

申请人： Dong-jun Kim ,  Jeong-hyuk Choi

发明人： Dong-jun Kim ,  Jeong-hyuk Choi

IPC分类号： G11C16/04 ,  G11C16/30 ,  H01L27/115 ,  G11C11/40 ,  G11C16/06

CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/30

摘要： Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect lines therein occupy less total area. With respect to integrated circuit memory devices containing NAND strings of EEPROM memory cells, the ground select electrodes for respective first and second pluralities of NAND strings (on a first side of a metal ground line) are joined together so that the number of ground select electrodes crossing the metal ground line can be reduced. The area normally occupied by the crossing ground select electrodes can then be used to interconnect the metal ground line to a substrate ground line using an interconnect via. Thus, the area normally reserved exclusively for the ground interconnect vias can be reduced or eliminated altogether by reducing the number of ground select electrodes which actually cross the metal ground line. In addition, to facilitate the connection of the metal ground line to the substrate ground line, depletion-mode transistors are formed in those areas where the ground select electrode(s) crosses the substrate ground line(s). The use of depletion-mode transistors prevents the formation of an electrical "open" between the substrate ground line and the metal ground line when the ground select electrodes are unbiased.

公开(公告)号：US20130200092A1

公开(公告)日：2013-08-08

申请号：US13570564

申请日：2012-08-09

申请人： Dong-jun KIM ,  In-hye Kim ,  Jung-hyeon Kim ,  Young-chai Heo

发明人： Dong-jun KIM ,  In-hye Kim ,  Jung-hyeon Kim ,  Young-chai Heo

IPC分类号： B65D25/10

CPC分类号： B65D75/24 ,  B65D81/025

摘要： A folding type package includes a body including first and second parts to face each other when the body is folded to enclose a product, at least one product housing part formed at the body, and a buffer part extending from the product housing part to secure a buffer space to buffer a shock applied to the product.

摘要翻译： 折叠式包装包括主体，其包括当主体被折叠以包围产品时的彼此面对的第一部分和第二部分，形成在主体上的至少一个产品收纳部分和从产品外壳部分延伸的缓冲部分 缓冲空间来缓冲产品的冲击。

公开(公告)号：US20120077307A1

公开(公告)日：2012-03-29

申请号：US13313306

申请日：2011-12-07

申请人： Dong Jun KIM ,  Kuninori Okamoto ,  Byung Chul Lee ,  Seok Hyun Jung

发明人： Dong Jun KIM ,  Kuninori Okamoto ,  Byung Chul Lee ,  Seok Hyun Jung

IPC分类号： H01L31/18 ,  C09K13/00

CPC分类号： C09K13/00 ,  H01L21/2225 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： An etching paste having a doping function for etching a thin film on a silicon wafer and a method of forming a selective emitter of a solar cell, the etching paste including an n-type or p-type dopant; a binder; and a solvent.

摘要翻译： 具有蚀刻硅晶片上的薄膜的掺杂功能的蚀刻膏和形成太阳能电池的选择性发射极的方法，所述蚀刻膏包括n型或p型掺杂剂; 粘合剂 和溶剂。

公开(公告)号：US20110192230A1

公开(公告)日：2011-08-11

申请号：US12984667

申请日：2011-01-05

申请人： Jin Woo NAM ,  Byung Joo Paek ,  Dong Jun Kim

发明人： Jin Woo NAM ,  Byung Joo Paek ,  Dong Jun Kim

IPC分类号： G01M7/02 ,  B06B3/00 ,  G01M7/08

CPC分类号： G01M7/027

摘要： A jig device usable with a flat display panel which includes a frame including a base frame having an opening and a vertical frame which extends vertically along a perimeter of the base frame and a supporting frame coupled to the base frame within the frame, on which the flat display panel is disposed, wherein the supporting frame includes fixing portions provided at corners thereof to support respective corners of the flat display panel.

摘要翻译： 一种可用于平板显示面板的夹具装置，其包括框架，该框架包括具有开口的基座框架和沿着所述底座框架的周边垂直延伸的垂直框架，以及支撑框架，其联接到所述框架内的所述基座框架， 平面显示面板设置在其中，支撑框架包括设置在其角部的固定部分，以支撑平面显示面板的各个角部。