公开(公告)号：US07436030B2

公开(公告)日：2008-10-14

申请号：US11463640

申请日：2006-08-10

申请人： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

发明人： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

摘要翻译： 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US20080179667A1

公开(公告)日：2008-07-31

申请号：US12099435

申请日：2008-04-08

申请人： Haining S. Yang ,  Wai-Kin Li

发明人： Haining S. Yang ,  Wai-Kin Li

IPC分类号： H01L29/76

CPC分类号： H01L21/28123 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

公开(公告)号：US20080122110A1

公开(公告)日：2008-05-29

申请号：US11555801

申请日：2006-11-02

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture is located within the passivation layer to expose the contact region. A corresponding narrow bottomed stepped sidewall contact via is located within the narrow bottomed stepped sidewall contact aperture to contact the contact region. The narrow bottomed stepped sidewall contact aperture and contact via provide for improved contact to the contact region and reduced parasitic capacitance with respect to the semiconductor device. Methods for fabricating the narrow bottomed stepped sidewall contact aperture use a mask layer (either dimensionally diminished or dimensionally augmented) in conjunction with a two step etch method.

摘要翻译： 半导体结构包括包括接触区域的半导体器件。 半导体结构还包括钝化层，钝化包括接触区域的半导体器件。 窄的有底阶梯式侧壁接触孔位于钝化层内以暴露接触区域。 相应的窄底部阶梯状侧壁接触通孔位于窄底部阶梯状侧壁接触孔内，以接触接触区域。 窄的有底阶梯式侧壁接触孔和接触通孔提供与接触区域的改善的接触并减小相对于半导体器件的寄生电容。 制造窄底阶阶侧壁接触孔的方法结合两步蚀刻方法使用掩模层（尺寸减小或尺寸增大）。

公开(公告)号：US20080036012A1

公开(公告)日：2008-02-14

申请号：US11463640

申请日：2006-08-10

申请人： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

发明人： Haining Yang ,  Thomas W. Dyer ,  Wai-Kin Li

IPC分类号： H01L29/76

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/481 ,  H01L23/485 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

摘要翻译： 公开了一种在分离的硅层上并入应变MOSFET的IC的制造方法和结构。 N沟道场效应晶体管（nFET）和P沟道FET（pFET）分别形成在分离的硅层上。 因此，可以形成与nFET和pFET相邻的浅沟槽绝缘（STI）区域，以对各个nFET和pFET的沟道区域产生不同的应力。 因此，通过STI应力可以提高nFET和pFET两者的性能。 此外，当两个硅层相对于彼此垂直地定位时，IC的面积也可以减小。

公开(公告)号：US20080020327A1

公开(公告)日：2008-01-24

申请号：US11458499

申请日：2006-07-19

申请人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

发明人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

IPC分类号： G03F7/26

CPC分类号： H01L21/76808

摘要： A method in which during the formation of damascene features in a semiconductor structure, a planarization material is added to vias formed in the dielectric to protect the vias during subsequent lithographic processing. The planarization material preferred is a developable photosensitive material which can be exposed and developed to define the damascene features rather than etching as is conventional.

摘要翻译： 一种在半导体结构中形成镶嵌特征的方法中，将平坦化材料添加到在电介质中形成的通孔中，以在随后的光刻处理期间保护通孔。 优选的平坦化材料是可显影的感光材料，其可以暴露和显影以限定镶嵌特征，而不是如常规的蚀刻。

公开(公告)号：US20070178404A1

公开(公告)日：2007-08-02

申请号：US11307268

申请日：2006-01-30

申请人： Colin J. Brodsky ,  Mary Jane Brodsky ,  Wai-Kin Li ,  Steven A. Scheer

发明人： Colin J. Brodsky ,  Mary Jane Brodsky ,  Wai-Kin Li ,  Steven A. Scheer

IPC分类号： G03C1/00

CPC分类号： G03F7/091

摘要： A method of forming a relief image on a substrate including: applying over a substrate a layer of an antireflective coating; and vacuum processing the antireflective coating. This method reduces the number of pinhole defects present in the antireflective coating.

摘要翻译： 一种在衬底上形成凸版图像的方法，包括：在衬底上涂覆抗反射涂层; 并对抗反射涂层进行真空处理。 该方法减少了抗反射涂层中存在的针孔缺陷的数量。

公开(公告)号：US20060199369A1

公开(公告)日：2006-09-07

申请号：US11069068

申请日：2005-03-01

申请人： Sajan Marokkey ,  O Park ,  Wai-Kin Li ,  Todd Bailey

发明人： Sajan Marokkey ,  O Park ,  Wai-Kin Li ,  Todd Bailey

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144

摘要： A method of preventing resist line collapse in damascene structures and a structure thereof is disclosed. A damascene pattern for resist lines is enhanced with ribs extending therefrom. The ribs provide mechanical support for resist lines and improve the lithography process for forming the resist lines, particularly when a negative focus is used. The ribs may extend between vias in an underlying material layer. The method results in structurally strong resist lines for damascene structures that are less likely to collapse.

公开(公告)号：US20050287488A1

公开(公告)日：2005-12-29

申请号：US11212989

申请日：2005-08-26

申请人： Kin Li

发明人： Kin Li

IPC分类号： F23Q2/16 ,  F23Q2/42 ,  F23Q7/12 ,  B67D5/00 ,  F23D14/28

CPC分类号： F23Q2/42 ,  F23Q2/161

摘要： A safety lighter includes a lighter body comprising a casing defining a liquefied gas chamber for containing a predetermined volume of liquefied gas therein, a supporting frame having an outer sealing surface engaged with an inner surface of the casing, a gas emitting nozzle mounted on the supporting frame to communicate with the liquefied gas chamber, and an ignition device supported by the supporting frame for ignition. A sealing arrangement includes upper and lower sealing rims spacedly and integrally provided along an opening portion of the inner surface of the casing in a step-shouldering manner wherein the upper and lower sealing rims are sealed with the outer sealing surface of the supporting frame to form two sealing lines along the upper and lower sealing rims respectively to sealedly mount the supporting frame on the lighter body for sealedly retaining the liquefied gas within the liquefied gas chamber.

摘要翻译： 一种安全打火机包括一个打火机，它包括一个限定液化气室的壳体，用于在其中容纳预定体积的液化气体，支撑框架具有与外壳的内表面相接合的外密封表面，安装在支撑件上的气体发射喷嘴 与液化气室连通的框架，以及由支撑框架支撑点火的点火装置。 密封装置包括上下密封边缘，其间隔地沿着壳体的内表面的开口部分一体地设置，其中上和下密封边缘用支撑框架的外密封表面密封以形成 分别沿着上下密封边缘的两条密封线将支撑框架密封地安装在打火机体上，以将液化气体密封地保持在液化气室内。

公开(公告)号：US5977715A

公开(公告)日：1999-11-02

申请号：US572390

申请日：1995-12-14

申请人： Kin Li ,  Minas Tanielian

发明人： Kin Li ,  Minas Tanielian

IPC分类号： H05B41/28 ,  H05H1/24 ,  H05H1/54 ,  H05B31/26

CPC分类号： H05H1/54 ,  H05B41/28 ,  H05H1/52

摘要： A handheld atmospheric pressure glow discharge plasma source is provided without the use of an arc. The plasma is induced using a radio frequency signal. An LC resonator in the handheld source with a gain of about 10 at 13.56 MHZ improves the power transfer from a power supply and tuner to the plasma chamber which is capable of producing stable plasmas in Ar, He and O.sub.2 mixtures.

摘要翻译： 提供手持式大气压辉光放电等离子体源，而不使用电弧。 使用射频信号感应等离子体。 手持式电源中的LC谐振器在13.56MHz时增益约为10，改善了从电源和调谐器到能够在Ar，He和O2混合物中产生稳定等离子体的等离子体室的功率传递。

公开(公告)号：US4996584A

公开(公告)日：1991-02-26

申请号：US257171

申请日：1988-10-13

申请人： Peter L. Young ,  Jay Cech ,  Kin Li

发明人： Peter L. Young ,  Jay Cech ,  Kin Li

IPC分类号： H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46

CPC分类号： H05K3/465 ,  H01L21/4846 ,  H01L23/147 ,  H01L23/538 ,  H05K3/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/242 ,  H05K3/244 ,  H05K3/388 ,  H05K3/4644

摘要： A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits (chips) is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planar surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.

摘要翻译： 描述了一种制造用于连接半导体集成电路（芯片）的薄膜多层互连信号面的方法。 在该方法中，在基板的表面上形成薄膜金属互连线的第一图案。 然后，在覆盖薄膜金属互连线图形的基板的整个表面上形成第一电介质层。 然后去除电介质层的一部分以暴露薄膜金属互连线，使得在每个互连线上方形成一系列沟槽。 然后将互连线电镀以形成一系列较厚的金属互连线，使得较厚的金属互连线和电介质层形成基本平坦的表面。 然后可以将该过程完全重复以形成多个互连信号平面。 在优选实施例中，为了电连接目的，金属通孔设置在每层金属互连线之间。