公开(公告)号：US20100321350A1

公开(公告)日：2010-12-23

申请号：US12785681

申请日：2010-05-24

Applicant: Ping-Lin Liu ,  Tse-Yuan Chen

Inventor： Ping-Lin Liu ,  Tse-Yuan Chen

IPC: G09G5/00

CPC classification number: G09G3/20 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A driving device outputting a plurality of sequentially asserted driving signals is provided, including a shift register, a buffer unit, and switch circuits. The shift register includes shift registering units coupled in series. The shift registering units respectively generate shift registering signals which are sequentially asserted. The buffer unit receives at least one input signal. The input signal is periodically asserted, and the buffer unit outputs the input signal. The switch circuits are coupled to the shift registering units to receive the shift registering signals, respectively. All of the switch circuits are coupled to the buffer unit to receive the input signal, and the switch circuits sequentially output the input signal to serve as the driving signals according to the assertion of the shift registering signals.

Abstract translation: 提供输出多个顺序断言的驱动信号的驱动装置，包括移位寄存器，缓冲单元和开关电路。 移位寄存器包括串联耦合的移位寄存单元。 移位登记单元分别产生顺序地被确认的移位登记信号。 缓冲单元接收至少一个输入信号。 周期性地输入输入信号，缓冲单元输出输入信号。 开关电路被耦合到移位寄存单元以分别接收移位寄存信号。 所有开关电路都耦合到缓冲单元以接收输入信号，并且开关电路根据移位寄存信号的断言顺序输出输入信号作为驱动信号。

公开(公告)号：US20080088547A1

公开(公告)日：2008-04-17

申请号：US11954257

申请日：2007-12-12

Applicant: Chuan-Yi Chan ,  Ping-Lin Liu ,  Du-Zen Peng

Inventor： Chuan-Yi Chan ,  Ping-Lin Liu ,  Du-Zen Peng

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0223 ,  G09G2320/0233

Abstract: A pixel driving circuit comprises a storage capacitor, a transistor, a transfer circuit, a driving element, and a switch circuit. The storage capacitor comprises first and second nodes. The transistor has a gate coupled to a discharge signal and is coupled between the first and second nodes. The discharge signal turns on the transistor in first and second discharge periods to discharge the storage capacitor. The transfer circuit outputs a data signal or a reference signal to the first node of the storage capacitor. The switch circuit is coupled to the driving element, a first display element and a second display element. The switch circuit can make the driving element diode-connected in first and second data load periods, and allow a driving current through a first display element in a first light-emitting period and a second display element in a second light-emitting period.

Abstract translation: 像素驱动电路包括存储电容器，晶体管，传输电路，驱动元件和开关电路。 存储电容器包括第一和第二节点。 晶体管具有耦合到放电信号的栅极，并耦合在第一和第二节点之间。 放电信号在第一和第二放电周期中导通晶体管，以放电存储电容器。 传送电路将数据信号或参考信号输出到存储电容器的第一节点。 开关电路耦合到驱动元件，第一显示元件和第二显示元件。 开关电路可以使驱动元件在第一和第二数据负载时段二极管连接，并且允许在第二发光周期中通过第一发光周期中的第一显示元件的驱动电流和第二显示元件的驱动电流。

公开(公告)号：US20080074164A1

公开(公告)日：2008-03-27

申请号：US11535499

申请日：2006-09-27

Applicant: Ping-Lin Liu

Inventor： Ping-Lin Liu

IPC: H03L5/00

CPC classification number: H03K19/01714

Abstract: A buffer circuit has a first transistor and a second transistor in a cascode, and a buffer switch coupled from an output of the buffer to a gate of the second transistor. The buffer circuit is bootstrapped by a bootstrap capacitor, a diode circuit, and a bootstrap switch. The bootstrap capacitor is coupled from the output to the gate of the second transistor through the bootstrap switch. A potential difference is set up across the bootstrap capacitor through the diode circuit. When a low input is given to the buffer circuit, the second transistor turns off and the output goes to a high bias voltage through the first transistor. When a high input is given, the first transistor turns off, the second transistor turns on, and as the output goes low, the gate of the second transistor is bootstrapped to drop the output completely down to a low bias voltage.

Abstract translation: 缓冲电路具有共源共栅中的第一晶体管和第二晶体管，以及从缓冲器的输出端耦合到第二晶体管的栅极的缓冲器开关。 缓冲电路由自举电容器，二极管电路和自举开关自举。 自举电容器通过自举开关从输出端耦合到第二晶体管的栅极。 通过二极管电路在自举电容器之间建立电位差。 当向缓冲器电路提供低输入时，第二晶体管截止，并且输出通过第一晶体管达到高偏置电压。 当给定高输入时，第一晶体管截止，第二晶体管导通，并且随着输出变低，第二晶体管的栅极被自举地将输出完全降低到低偏置电压。

公开(公告)号：US20070262931A1

公开(公告)日：2007-11-15

申请号：US11801162

申请日：2007-05-08

Applicant: Du Zen Peng ,  Ping-Lin Liu

Inventor： Du Zen Peng ,  Ping-Lin Liu

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0223 ,  G09G2320/0233

Abstract: A pixel driving circuit with threshold voltage and power supply voltage compensation. The pixel circuit includes a storage capacitor, a transistor, a transfer circuit, a driving element, and a switching circuit. The transistor has a gate coupled to a discharge signal and is coupled between a first node and a second node. The discharge signal directs the transistor to turn on and then discharges the storage capacitor in a first period. The transfer circuit transfers a data signal or a reference signal to a first node of the storage capacitor. The driving element has a first terminal coupled to a first voltage, a second terminal coupled to a second node of the storage capacitor and a third terminal outputting a driving current. The switching circuit is coupled between the driving element and a display element. The switching circuit can be controlled to diode-connect the driving element in a second period, allowing the driving current to be output to the display element in a third time period.

Abstract translation: 具有阈值电压和电源电压补偿的像素驱动电路。 像素电路包括存储电容器，晶体管，传输电路，驱动元件和开关电路。 晶体管具有耦合到放电信号的栅极，并且耦合在第一节点和第二节点之间。 放电信号引导晶体管导通，然后在第一周期内放电存储电容器。 传送电路将数据信号或参考信号传送到存储电容器的第一节点。 驱动元件具有耦合到第一电压的第一端子，耦合到存储电容器的第二节点的第二端子和输出驱动电流的第三端子。 开关电路耦合在驱动元件和显示元件之间。 可以控制开关电路以在第二时间段内对驱动元件进行二极管连接，从而允许在第三时间段内将驱动电流输出到显示元件。