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63 条记录 (耗时 0.014 秒)

    Low power manager for standby operation of memory system
    31.
    发明授权
    Low power manager for standby operation of memory system 有权
    低功耗管理器用于存储系统的待机操作

    公开(公告)号：US07046572B2

    公开(公告)日：2006-05-16

    申请号：US10250233

    申请日：2003-06-16

    申请人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    发明人： David R. Hansen ,  Gregory J. Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

    IPC分类号： G11C7/00

    CPC分类号： G11C5/143 ,  G11C8/08

    摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

    摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

    Self-aligned contact for closely spaced transistors
    33.
    发明授权
    Self-aligned contact for closely spaced transistors 失效
    紧密间隔晶体管的自对准触点

    公开(公告)号：US06294449B1

    公开(公告)日：2001-09-25

    申请号：US09447627

    申请日：1999-11-23

    申请人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

    发明人： Teresa J. Wu ,  Bomy A. Chen ,  John W. Golz ,  Charles W. Koburger, III ,  Paul C. Parries ,  Christopher J. Waskiewicz ,  Jin Jwang Wu

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897

    摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

    摘要翻译： 一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT
    38.
    发明申请
    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT 失效
    通过门式井口植入降低阈值电压变化的方法

    公开(公告)号：US20120326233A1

    公开(公告)日：2012-12-27

    申请号：US13608860

    申请日：2012-09-10

    申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

    摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

    摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部内。

    Method of Fabricating Isolated Capacitors and Structure Thereof
    39.
    发明申请
    Method of Fabricating Isolated Capacitors and Structure Thereof 有权
    制造隔离电容器及其结构的方法

    公开(公告)号：US20120267754A1

    公开(公告)日：2012-10-25

    申请号：US13533099

    申请日：2012-06-26

    申请人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

    发明人： Oh-Jung KWON ,  Junedong LEE ,  Paul C. PARRIES ,  Dominic J. SCHEPIS

    IPC分类号： H01L29/92

    CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

    摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

    摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

    SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS
    40.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS 失效
    具有不同材料的宽度和深度深度的半导体结构

    公开(公告)号：US20120122303A1

    公开(公告)日：2012-05-17

    申请号：US12943973

    申请日：2010-11-11

    申请人： PAUL C. PARRIES ,  Yanli Zhang

    发明人： PAUL C. PARRIES ,  Yanli Zhang

    IPC分类号： H01L21/302 ,  H01L21/762

    CPC分类号： H01L21/76229

    摘要： Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.

    摘要翻译： 公开了一种在半导体层中形成半导体器件结构的方法。 该方法包括在半导体层中形成第一宽度的第一沟槽和第二宽度的第二沟槽; 沉积符合第一沟槽的壁但不填充它并填充第二沟槽的第一材料层; 从第一沟槽去除第一材料，第一材料残留在第二沟槽中; 在所述第二沟槽中沉积第二材料并填充所述第一沟槽并且覆盖所述第一材料的顶部; 并且从所述第二沟槽中的所述第一材料的顶部均匀地去除所述第二材料，其中所述第一沟槽被所述第二材料填充，并且所述第二沟槽被所述第一材料填充，并且其中所述第一材料与所述第二材料不同。