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43 条记录 (耗时 0.028 秒)

    Fast, symmetrical XOR/XNOR gate
    31.
    发明授权
    Fast, symmetrical XOR/XNOR gate 有权
    快速对称XOR / XNOR门

    公开(公告)号：US06573758B2

    公开(公告)日：2003-06-03

    申请号：US09965006

    申请日：2001-09-27

    申请人： David William Boerstler ,  Juan Antonio Carballo ,  Robert Kevin Montoye

    发明人： David William Boerstler ,  Juan Antonio Carballo ,  Robert Kevin Montoye

    IPC分类号： H03K19094

    CPC分类号： H03K19/215

    摘要： In one aspect, circuitry for a digital logic function includes a first pair of input nodes for receiving respective first and second input signals, a second pair of input nodes for receiving respective complements of the first and second input signals, and an output node. The circuitry has a plurality of PFET-NFET pass gates. Such a pass gate has a first conducting electrode of the pass gate PFET connected to a first conducting electrode of the pass gate NFET, providing a first conducting node of the pass gate, and a second conducting electrode of the pass gate PFET connected to a second conducting electrode of the pass gate NFET, providing a second conducting node of the pass gate. The input nodes are connected to first conducting nodes of respective ones of the plurality of pass gates, and the second conducting nodes of the plurality of pass gates are connected to the circuitry output node.

    摘要翻译： 在一个方面，用于数字逻辑功能的电路包括用于接收相应的第一和第二输入信号的第一对输入节点，用于接收第一和第二输入信号的相应补码的第二对输入节点和输出节点。 该电路具有多个PFET-NFET通孔。 这样的栅极具有连接到栅极NFET的第一导电电极的栅极PFET的第一导电电极，提供栅极的第一导电节点，以及连接到第二栅极PFET的栅极PFET的第二导电电极 传导门NFET的导电电极，提供通孔的第二导电节点。 所述输入节点连接到所述多个通过门中的相应传导门的第一导电节点，并且所述多个通路中的所述第二导通节点连接到所述电路输出节点。

    System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation
    36.
    发明申请
    System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation 审中-公开
    双速定时脉冲发生系统和方法，具有消除干扰

    公开(公告)号：US20100266081A1

    公开(公告)日：2010-10-21

    申请号：US12427218

    申请日：2009-04-21

    申请人： Gary S. Ditlow ,  Robert Kevin Montoye ,  Salvatore Nicholas Storino

    发明人： Gary S. Ditlow ,  Robert Kevin Montoye ,  Salvatore Nicholas Storino

    IPC分类号： H04L7/00

    CPC分类号： G06F1/10

    摘要： A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer.

    摘要翻译： 一种用于产生双速率时钟电路的方法，该方法包括通过至少一个反相器电路将第一本地时钟缓冲器的输出端耦合到第二本地时钟缓冲器的输入，并用基本信号驱动第一本地时钟缓冲器。 该方法还包括基于基本信号产生具有第一本地时钟缓冲器的早期时钟信号，并通过用至少一个反相器延迟第一本地时钟信号来产生延迟的早期时钟信号。 该方法还包括通过用延迟的早期时钟信号驱动第二本地时钟缓冲器来产生较后的时钟信号，其中由第二本地时钟缓冲器产生的第二本地时钟缓冲器和后期时钟信号同步并与第一本地时钟缓冲器相关联 和由第一本地时钟缓冲器产生的早期时钟信号。

    Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
    39.
    发明授权
    Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock 失效
    具有由电压非对称时钟分别控制的预充电元件的动态逻辑电路

    公开(公告)号：US07282960B2

    公开(公告)日：2007-10-16

    申请号：US11168718

    申请日：2005-06-28

    申请人： Wendy Ann Belluomini ,  Robert Kevin Montoye ,  Aniket Mukul Saha

    发明人： Wendy Ann Belluomini ,  Robert Kevin Montoye ,  Aniket Mukul Saha

    IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/0175 ,  H03K19/096

    CPC分类号： H03K19/0963

    摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

    摘要翻译： 具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。 通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，以防止门的动态求和节点由于 噪音，并且消除了对保持装置的需要。 将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。 具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。 电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

    Method and apparatus for performing bit-aligned permute
    40.
    发明授权
    Method and apparatus for performing bit-aligned permute 失效
    用于执行位对齐排列的方法和装置

    公开(公告)号：US07014122B2

    公开(公告)日：2006-03-21

    申请号：US10745730

    申请日：2003-12-24

    申请人： Ramyanshu Datta ,  Robert Kevin Montoye

    发明人： Ramyanshu Datta ,  Robert Kevin Montoye

    IPC分类号： G06K19/06

    CPC分类号： G06F7/76

    摘要： A method and apparatus for performing bit-aligned permute are disclosed. A select register, a pair of data registers and a target register are provided. The entries of the select register is preloaded with a set of bit indices. Each of the bit indices points to a desired bit location within the data registers. The byte information stored in the data registers are then copied to the target register according to the bit indices within the select register.

    摘要翻译： 公开了一种用于执行位对齐排列的方法和装置。 提供一个选择寄存器，一对数据寄存器和一个目标寄存器。 选择寄存器的条目预先加载一组位索引。 每个比特索引指向数据寄存器内的所需比特位置。 存储在数据寄存器中的字节信息然后根据选择寄存器中的位索引被复制到目标寄存器。