公开(公告)号：US08737554B2

公开(公告)日：2014-05-27

申请号：US13326205

申请日：2011-12-14

申请人： Seong-Do Kim ,  Pil Jae Park ,  Sung Chul Woo ,  Hyun Kyu Yu

发明人： Seong-Do Kim ,  Pil Jae Park ,  Sung Chul Woo ,  Hyun Kyu Yu

IPC分类号： H04L7/00

CPC分类号： G01S7/2921 ,  H03M1/1215 ,  H03M1/1265

摘要： Disclosed is a pulse-signal recovering device with a time-interleaving scheme. Exemplary embodiments of the present invention can improve receive performance of a radar so as to shorten pre-scanning time for roughly determining presence and absence of objects and time consumed to recover received pulse signals in the radar receiver with the sub-sampling scheme by simultaneously sensing signal levels of the received pulse signals at several positions and improve a signal to noise ratio by increasing an averaging rate with respect to the number of same received pulses.

摘要翻译： 公开了一种具有时间交织方案的脉冲信号恢复装置。 本发明的示例性实施例可以改善雷达的接收性能，以便缩短预扫描时间，以大致确定物体的存在和不存在以及利用子采样方案通过同时感测在雷达接收机中恢复接收到的脉冲信号所消耗的时间 在几个位置处接收到的脉冲信号的信号电平，并通过相对于相同的接收脉冲的数量增加平均速率来提高信噪比。

公开(公告)号：US20120148002A1

公开(公告)日：2012-06-14

申请号：US13326205

申请日：2011-12-14

申请人： Seong-Do KIM ,  Pil Jae Park ,  Sung Chul Woo ,  Hyun Kyu Yu

发明人： Seong-Do KIM ,  Pil Jae Park ,  Sung Chul Woo ,  Hyun Kyu Yu

IPC分类号： H04L7/00

CPC分类号： G01S7/2921 ,  H03M1/1215 ,  H03M1/1265

摘要： Disclosed is a pulse-signal recovering device with a time-interleaving scheme. Exemplary embodiments of the present invention can improve receive performance of a radar so as to shorten pre-scanning time for roughly determining presence and absence of objects and time consumed to recover received pulse signals in the radar receiver with the sub-sampling scheme by simultaneously sensing signal levels of the received pulse signals at several positions and improve a signal to noise ratio by increasing an averaging rate with respect to the number of same received pulses.

摘要翻译： 公开了一种具有时间交织方案的脉冲信号恢复装置。 本发明的示例性实施例可以改善雷达的接收性能，以便缩短预扫描时间，以大致确定物体的存在和不存在以及利用子采样方案通过同时感测在雷达接收机中恢复接收到的脉冲信号所消耗的时间 在几个位置处接收到的脉冲信号的信号电平，并通过相对于相同的接收脉冲的数量增加平均速率来提高信噪比。

公开(公告)号：US20110237759A1

公开(公告)日：2011-09-29

申请号：US13133003

申请日：2009-03-19

申请人： Seong-Do Kim ,  Taehoung Jeong ,  Tae-Byoung Oh

发明人： Seong-Do Kim ,  Taehoung Jeong ,  Tae-Byoung Oh

IPC分类号： C08L67/02 ,  C08G63/183 ,  C08J5/18

CPC分类号： C08J5/18 ,  C08J2367/02 ,  Y10T428/1328 ,  Y10T428/31786

摘要： A heat-shrinkable polyester film having a thermal shrinkage ratio of 15% or more in the longitudinal direction when treated at 100° C. for 10 seconds, a tensile strength at rupture in the longitudinal direction of 7 kgf/mm2 or more, and a difference between elongations at the hardening and yield points in the longitudinal direction of 15% or more exhibits superior properties, such as high tensile strength and crack-resistance in the longitudinal direction, suitable for labeling or shrink-wrapping containers.

摘要翻译： 在100℃下处理10秒钟时，纵向的热收缩率为15％以上的热收缩性聚酯膜，长度方向的断裂拉伸强度为7kgf / mm 2以上， 在纵向上的硬化和屈服点的伸长率之间的差异在15％以上表现出优异的性能，例如长度方向上的高拉伸强度和抗裂性，适用于标签或收缩包装容器。

公开(公告)号：US20110224369A1

公开(公告)日：2011-09-15

申请号：US13041831

申请日：2011-03-07

申请人： Seong Do KIM ,  Tae Byoung OH ,  Tae Houng JEONG

发明人： Seong Do KIM ,  Tae Byoung OH ,  Tae Houng JEONG

IPC分类号： C08L67/02 ,  B29C47/00 ,  C08G63/672 ,  C08G63/183

CPC分类号： C08J5/18 ,  B29C47/0021 ,  B29C47/0057 ,  B29C55/04 ,  B29C61/003 ,  B29C63/38 ,  B29K2067/00 ,  B29K2105/02 ,  C08G63/183 ,  C08J2367/02 ,  C09D5/26 ,  Y10T428/1328 ,  Y10T428/1331 ,  Y10T428/31786

摘要： A heat-shrinkable polyester film having a heat-shrinkage change per degree Celsius (%/° C.) along the main shrinkage direction of 1.5 to 3.0 in the range of 60° C. to 70° C., 2.5 to 3.5 in the range of 70° C. to 80° C., 1.0 to 2.0 in the range of 80° C. to 90° C., and 0.1 to 1.0 in the range of 90° C. to 100° C., has a good appearance quality after shrinkage and thus suitable for a wrapping material, particularly a label for a bottle.

摘要翻译： 沿着主收缩方向的热收缩率变化为每摄氏度（％/℃）为1.5〜3.0的热收缩性聚酯膜为60〜70℃，2.5〜3.5 在80℃至80℃的范围内，在80℃至90℃的范围内为1.0至2.0，在90℃至100℃的范围内为0.1至1.0，具有良好的 收缩后的外观质量因此适合于包装材料，特别是瓶子的标签。

公开(公告)号：US20110202302A1

公开(公告)日：2011-08-18

申请号：US13027462

申请日：2011-02-15

申请人： Pil Jae PARK ,  Hyun Kyu Yu ,  Seong Do Kim ,  Sung Chul Woo

发明人： Pil Jae PARK ,  Hyun Kyu Yu ,  Seong Do Kim ,  Sung Chul Woo

IPC分类号： G06F15/00 ,  G01S13/58 ,  G01S15/58 ,  H04N5/33

CPC分类号： G01S13/886 ,  G08B13/19613 ,  G08B29/185

摘要： An apparatus and method for identifying a human being and an animal are disclosed to properly identifying whether or not a target is a human being or an animal. The apparatus for distinguishing between a human being and an animal includes: a target stimulation unit generating a stimulation signals for selectively stimulating the senses of a human being and an animal and providing the generated stimulation signal to a target; and a target identifying unit detecting the reaction of a target to the simulation signal to identify whether or not the target is a human being or an animal.

摘要翻译： 公开了用于识别人和动物的装置和方法，以适当地识别目标是否是人或动物。 用于区分人和动物的装置包括：目标刺激单元，其产生用于选择性地刺激人和动物的感觉并将产生的刺激信号提供给目标的刺激信号; 以及目标识别单元，其检测目标对所述模拟信号的反应，以识别所述目标是人类还是动物。

公开(公告)号：US20110150138A1

公开(公告)日：2011-06-23

申请号：US12970899

申请日：2010-12-16

申请人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

发明人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

IPC分类号： H03K9/00

CPC分类号： H04L25/08 ,  H03D7/1441 ,  H03D7/1458 ,  H03H19/004

摘要： A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

摘要翻译： 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。

公开(公告)号：US20110150125A1

公开(公告)日：2011-06-23

申请号：US12968731

申请日：2010-12-15

申请人： Hyun Kyu YU ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

发明人： Hyun Kyu YU ,  Jang Hong Choi ,  Hyun Ho Boo ,  Pil Jae Park ,  Mun Yang Park ,  Seong Do Kim ,  Sun Bo Shim ,  Song Cheol Hong

IPC分类号： H04L27/00 ,  H03M3/02 ,  H03M1/66

CPC分类号： H03M1/68 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747 ,  H03M3/50

摘要： There are provided a digital RF converter capable of improving a dynamic range and a signal to noise ratio of a transmitter and a digital RF modulator and a transmitter including the same. The digital RF converter may include: a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed; a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed; and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

摘要翻译： 提供了能够改善发射机和数字RF调制器的动态范围和信噪比的数字RF转换器，以及包括该数字RF转换器的发射机。 数字RF转换器可以包括：Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号中产生对应于最低有效n比特的电流幅度; 最低有效位（LSB）子块，其以比第一采样速度低的第二采样速度在输入信号中产生对应于中间k位的电流幅度; 和最高有效位（MSB）子块，其以第二采样速度在输入信号中产生对应于最高有效m位的电流幅度。

公开(公告)号：US20110148490A1

公开(公告)日：2011-06-23

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08 ,  H03M1/50

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US20100134192A1

公开(公告)日：2010-06-03

申请号：US12581105

申请日：2009-10-16

申请人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

发明人： Byung Hun MIN ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/00

CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.

摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值 的振荡器。

公开(公告)号：US20070241844A1

公开(公告)日：2007-10-18

申请号：US11690219

申请日：2007-03-23

申请人： Cheon Soo KIM ,  Myung Shin KWAK ,  Seong Do KIM ,  Mun Yang PARK ,  Hyun Kyu YU ,  Hee Bum JUNG

发明人： Cheon Soo KIM ,  Myung Shin KWAK ,  Seong Do KIM ,  Mun Yang PARK ,  Hyun Kyu YU ,  Hee Bum JUNG

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。