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    METHODS OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE
    31.
    发明申请
    METHODS OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE 有权
    制造磁阻随机访问存储器件的方法

    公开(公告)号：US20150236251A1

    公开(公告)日：2015-08-20

    申请号：US14533084

    申请日：2014-11-04

    Applicant: Eun-Sun NOH ,  Jong-Chul PARK ,  Shin KWON ,  Hyung-Joon KWON ,  Chae-Lyoung KIM ,  Hye-Ji YOON

    Inventor： Eun-Sun NOH ,  Jong-Chul PARK ,  Shin KWON ,  Hyung-Joon KWON ,  Chae-Lyoung KIM ,  Hye-Ji YOON

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

    CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

    Abstract: In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures. Each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, and each of the MTJ structures contacts a corresponding one of the lower electrodes.

    Abstract translation: 在制造MRAM器件的方法中，第一牺牲层，蚀刻停止层和第二牺牲层依次形成在衬底上，然后被部分蚀刻以形成通过其的开口。 形成下电极以填充开口。 去除第一和第二牺牲层和蚀刻停止层的部分以分别形成围绕下部电极的侧壁的上部的蚀刻停止层图案。 在蚀刻停止层图案之间形成上部绝缘层图案，以在下部电极之间部分地限定气垫。 形成第一磁性层，隧道势垒层，第二磁性层和上电极层，并被蚀刻以形成多个磁性隧道结（MTJ）结构。 每个MTJ结构包括顺序堆叠的第一磁性层图案，隧道层图案和第二磁性层图案，并且每个MTJ结构接触相应的一个下部电极。

    Method of improving gate resistance in a memory array
    34.
    发明授权
    Method of improving gate resistance in a memory array 失效
    提高存储器阵列中栅极电阻的方法

    公开(公告)号：US07696048B2

    公开(公告)日：2010-04-13

    申请号：US11425065

    申请日：2006-06-19

    Applicant: Hyung-Shin Kwon ,  Seug-Gyu Kim

    Inventor： Hyung-Shin Kwon ,  Seug-Gyu Kim

    IPC: H01L21/8232 ,  H01L21/8239

    CPC classification number: H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

    Abstract: A semiconductor device is formed with a normal, non-recessed, spacer structure in a cell region and a recessed spacer structure in a peripheral region. The recessed spacer structure is formed as by etch masking those in the cell region and exposing those in the peripheral region, then performing an etch process. The increased height of the cell region spacers is adapted to further prevent over-etching during gate interconnect formation which would otherwise result in etching through the spacer to the substrate and subsequent short circuit. Therefore, it is also possible to prevent bridge defects due to over-etching, which occurs because the barrier metal layer for a subsequent interconnection contact is accidentally connected to the underlying substrate. Also, since the recessed spacer structure is provided in the peripheral region, it is possible to remarkably enhance a resistance distribution of a cobalt silicide layer occurring in a gate line width of 100 nm or less.

    Abstract translation: 半导体器件在单元区域中具有正常的非凹入的间隔结构，并且在周边区域中形成有凹入的间隔结构。 凹陷的间隔结构通过蚀刻掩蔽细胞区域中的那些并且暴露在外围区域中的那些，然后进行蚀刻工艺而形成。 单元区域间隔物的增加的高度适于进一步防止在栅极互连形成期间的过度蚀刻，否则将导致通过间隔物蚀刻到衬底和随后的短路。 因此，也可以防止由于用于随后的互连接触的阻挡金属层意外地连接到下面的基板而发生的由于过蚀刻而引起的桥接缺陷。 此外，由于在周边区域设置凹陷的间隔结构，因此可以显着提高出现在100nm以下的栅极线宽度的硅化钴层的电阻分布。

    Image pickup device with non-molded DSP chip and manufacturing method
    36.
    发明授权
    Image pickup device with non-molded DSP chip and manufacturing method 有权
    具有非模制DSP芯片的图像拾取器件及其制造方法

    公开(公告)号：US07405760B2

    公开(公告)日：2008-07-29

    申请号：US10347184

    申请日：2003-01-21

    Applicant: Min Kyo Cho ,  Sa Yoon Kang ,  Young Hoon Ro ,  Young Shin Kwon

    Inventor： Min Kyo Cho ,  Sa Yoon Kang ,  Young Hoon Ro ,  Young Shin Kwon

    IPC: H04N5/225

    CPC classification number: H04N5/2253 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/92247 ,  H01L2924/00014

    Abstract: An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.

    Abstract translation: 一种摄像装置及其制造方法。 数字信号处理（DSP）芯片附着在基板的第一表面上。 CMOS图像传感器（CIS）芯片附着在DSP芯片的有源表面上。 DSP芯片和CIS芯片可以通过引线接合电连接到基板。 具有被配置为将图像传送到DSP芯片的透镜的外壳套件可以安装在基板上。 外壳套件和基板之间的内部空间不被模制，从而简化制造过程并提供更薄和/或更轻的图像拾取装置。

    Semiconductor device having silicide thin film and method of forming the same
    37.
    发明授权
    Semiconductor device having silicide thin film and method of forming the same 有权
    具有硅化物薄膜的半导体器件及其形成方法

    公开(公告)号：US07385260B2

    公开(公告)日：2008-06-10

    申请号：US10830390

    申请日：2004-04-21

    Applicant: Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

    Inventor： Hyung-Shin Kwon ,  Joon-Yong Joo ,  Kwang-Ok Koh ,  Sung-Bong Kim

    IPC: H01L29/861

    CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

    Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

    Abstract translation: 本发明提供一种具有硅化物薄膜的半导体器件及其形成方法。 半导体器件包括形成在半导体衬底的有源区上的栅极绝缘层。 在栅极绝缘层上形成栅电极。 在与栅电极相邻的有源区中形成杂质区。 诸如硅化钴薄膜的硅化物薄膜在杂质区域中形成为小于约200埃的厚度。

    Method for fabricating a MOS transistor using a self-aligned silicide technique
    39.
    发明授权
    Method for fabricating a MOS transistor using a self-aligned silicide technique 失效

    公开(公告)号：US06635539B2

    公开(公告)日：2003-10-21

    申请号：US10131418

    申请日：2002-04-22

    Applicant: Hyung-Shin Kwon ,  Do-Hyung Kim

    Inventor： Hyung-Shin Kwon ,  Do-Hyung Kim

    IPC: H01L21336

    CPC classification number: H01L29/66507 ,  H01L29/66545

    Abstract: A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode. Therefore, it is possible to fabricate a high-performance MOS transistor suitable for a highly integrated semiconductor device.

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