公开(公告)号：US6040605A

公开(公告)日：2000-03-21

申请号：US236630

申请日：1999-01-26

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  G11C2216/08

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US5960266A

公开(公告)日：1999-09-28

申请号：US878206

申请日：1997-06-18

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L27/115 ,  H01L27/12 ,  H01L29/68 ,  H01L29/788 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A quantum semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is resistant to interference from noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile quantum memory device can be realized with reduced size.

摘要翻译： 公开了一种量子半导体存储元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且能够抵抗来自噪声的干扰。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性量子存储器件。

公开(公告)号：US20120248422A1

公开(公告)日：2012-10-04

申请号：US13432678

申请日：2012-03-28

申请人： Toshiyuki MINE ,  Masaaki Fujimori ,  Naofumi Ohashi

发明人： Toshiyuki MINE ,  Masaaki Fujimori ,  Naofumi Ohashi

IPC分类号： H01L51/52 ,  H01L51/56

CPC分类号： H01L51/5256

摘要： In a device having an anode electrode, an organic EL layer, and a cathode electrode formed on a substrate in this order from a main surface side of the substrate, and an encapsulating film provided on the substrate so as to cover the emission layer, the encapsulating film includes a laminated film obtained by alternately laminating buffer films serving as flattening films and barrier films having high moisture barrier property, and the flattening film and the barrier film include a silicon oxynitride film. In the manufacturing process of the device, the buffer film including silicon oxynitride is formed by an optical CVD method using vacuum ultraviolet light, and in this process, radical irradiation by remote plasma is performed during the irradiation of the vacuum ultraviolet light.

摘要翻译： 在从衬底的主表面侧依次形成在基板上的阳极电极，有机EL层和阴极电极的装置以及设置在基板上以覆盖发光层的封装膜， 封装膜包括通过交替层叠用作平坦化膜的缓冲膜和具有高阻隔性的阻挡膜获得的层压膜，并且该平坦化膜和阻挡膜包括氧氮化硅膜。 在该装置的制造工序中，通过使用真空紫外光的光CVD法形成包含氮氧化硅的缓冲膜，在该过程中，在真空紫外光的照射期间进行远程等离子体的自由基照射。

公开(公告)号：US20120211718A1

公开(公告)日：2012-08-23

申请号：US13440225

申请日：2012-04-05

申请人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08125012B2

公开(公告)日：2012-02-28

申请号：US11639134

申请日：2006-12-15

申请人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

发明人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42344 ,  H01L29/512 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

摘要翻译： 通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。 通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。 通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。 在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。 电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

公开(公告)号：US07863134B2

公开(公告)日：2011-01-04

申请号：US12695271

申请日：2010-01-28

申请人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

发明人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US20100129998A1

公开(公告)日：2010-05-27

申请号：US12695271

申请日：2010-01-28

申请人： Hirotaka HAMAMURA ,  Itaru YANAGI ,  Toshiyuki MINE

发明人： Hirotaka HAMAMURA ,  Itaru YANAGI ,  Toshiyuki MINE

IPC分类号： H01L21/28

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US07682990B2

公开(公告)日：2010-03-23

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20090267047A1

公开(公告)日：2009-10-29

申请号：US12430539

申请日：2009-04-27

申请人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

发明人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

IPC分类号： H01L47/00

CPC分类号： H01L27/2481 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

摘要： The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.

摘要翻译： 本发明可以通过实现半导体器件和存储器件的高性能来促进半导体存储器件的大容量，高性能和高可靠性，当半导体存储器件通过堆叠诸如ReRAM的存储器件或 相变存储器和半导体器件。 在低温下以非晶态沉积形成选择器件的多晶硅后，通过激光退火的热处理来简单地进行多晶硅的结晶化和杂质的活化。 当进行激光退火时，位于被结晶的硅下方的记录材料完全被金属膜或金属膜和绝缘膜覆盖，从而可以抑制进行退火时的温度升高 并降低记录材料的热负荷。

公开(公告)号：US20090134449A1

公开(公告)日：2009-05-28

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。