公开(公告)号：US4887083A

公开(公告)日：1989-12-12

申请号：US167235

申请日：1988-03-11

申请人： Toru Kosugi ,  Takahiro Furukawa ,  Hirohisa Miyaou

发明人： Toru Kosugi ,  Takahiro Furukawa ,  Hirohisa Miyaou

IPC分类号： H03M5/16 ,  H04L25/49

CPC分类号： H04L25/4925

摘要： A B8ZS.B6ZS coding circuit commonly used for a B8ZS coding or a B6ZS coding, generating a B8ZS violation signal or a B6ZS violation signal at a same start timing, and formed by a smaller circuit. The B8ZS.B6ZS coding circuit includes a first eight-bit shift register, receiving the input unipolar signal and shifting the same in response to a clock signal, the last two flip-flops in the shift register being reset under the B6ZS mode, a first gate outputting a first consecutive zero detection signal when all flip-flops in the first shift register are reset, a second seven-bit shift register, the last two flip-flops in the shift register being reset under the B6ZS mode, a second gate outputting a second consecutive zero detection signal when all flip-flops in the second shift register are reset, a third gate outputting an exclusive OR signal of the first and the second consecutive zeros detection signals, an inverter and outputting an inverted signal of the output from the third gate, a fourth gate receiving outputs from a sixth flip-flop in the first shift register, first, second, fourth and fifth flip-flops in the second shift register, and outputting a first original coded signal, and a fifth gate receiving outputs from the sixth flip-flop in the first shift register, the inverter, and the first, fourth and fifth flip-flops in the second shift register, and outputting a second original coded signal.