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    Method and Apparatus to Reduce Impedance Discontinuity in Packages
    32.
    发明申请
    Method and Apparatus to Reduce Impedance Discontinuity in Packages 失效
    减少封装阻抗不连续性的方法和装置

    公开(公告)号：US20090126983A1

    公开(公告)日：2009-05-21

    申请号：US11942061

    申请日：2007-11-19

    申请人： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

    发明人： Paul M. Harvey ,  Douglas O. Powell ,  Wolfgang Sauter ,  Yaping Zhou

    IPC分类号： H05K1/02 ,  H05K3/10

    CPC分类号： H05K1/115 ,  H05K1/0233 ,  H05K1/112 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/096

    摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

    摘要翻译： 一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。 迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP
    35.
    发明申请
    SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP 失效
    具有降低应力的半导体芯片

    公开(公告)号：US20090032929A1

    公开(公告)日：2009-02-05

    申请号：US11830228

    申请日：2007-07-30

    申请人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    发明人： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

    IPC分类号： H01L23/24 ,  H01L21/00

    CPC分类号： H01L23/3192 ,  H01L21/563 ,  H01L23/3178 ,  H01L2224/73203 ,  H01L2924/01079

    摘要： Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

    摘要翻译： 用于形成它的结构和方法。 半导体芯片包括半导体衬底和半导体衬底上的晶体管。 该芯片还包括在半导体衬底之上的N个互连层，并且电耦合到晶体管，N是正整数。 芯片还包括在N个互连层的顶部上的第一介电层，以及在第一介电层的顶部上的第二介电层。 第二电介质层与N互连层的每个互连层直接物理接触。 芯片还包括在第二电介质层顶部的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。 芯片还包括在底部填充层顶部的层压基板。 底部填充层被夹在第二介电层和层叠基板之间。