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31.发明申请GRAPHICS PROCESSING HARDWARE FOR USING COMPUTE SHADERS AS FRONT END FOR VERTEX SHADERS 审中-公开使用COMPUTE SHADERS作为前端用于VERTEX SHADERS的图形处理硬件公开(公告)号：US20140362102A1
公开(公告)日：2014-12-11
申请号：US14297290
申请日：2014-06-05
Inventor： Mark Evan Cerny , David Simpson , Jason Scanlin , Michael Mantor
IPC: G06T1/20
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A GPU is configured to read and process data produced by a compute shader via the one or more ring buffers and pass the resulting processed data to a vertex shader as input. The GPU is further configured to allow the compute shader and vertex shader to write through a cache. Each ring buffer is configured to synchronize the compute shader and the vertex shader to prevent processed data generated by the compute shader that is written to a particular ring buffer from being overwritten before the data is accessed by the vertex shader. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Abstract translation: GPU被配置为通过一个或多个环形缓冲器读取和处理由计算着色器产生的数据，并将所得到的处理后的数据传递给顶点着色器作为输入。 GPU进一步配置为允许计算着色器和顶点着色器通过高速缓存进行写入。 每个环形缓冲区被配置为使计算着色器和顶点着色器同步，以防止在由顶点着色器访问数据之前被写入特定环形缓冲区的计算着色器生成的被处理数据被覆盖。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。
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公开(公告)号：US20240193844A1
公开(公告)日：2024-06-13
申请号：US18077424
申请日：2022-12-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Fowler , Samuel Naffziger , Michael Mantor , Mark Leather
CPC classification number: G06T15/005 , G06F9/3802
Abstract: A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.
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公开(公告)号：US11954036B2
公开(公告)日：2024-04-09
申请号：US17985674
申请日：2022-11-11
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan S. Jayasena , James Michael O'Connor , Michael Mantor
IPC: G06F12/0862 , G06F8/41 , G06F9/52
CPC classification number: G06F12/0862 , G06F8/4442 , G06F9/52 , Y02D10/00
Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.
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公开(公告)号：US11803385B2
公开(公告)日：2023-10-31
申请号：US17548105
申请日：2021-12-10
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sateesh Lagudu , Arun Vaidyanathan Ananthanarayan , Michael Mantor , Allen H. Rush
CPC classification number: G06F9/321 , G06F9/3004 , G06F9/30087 , G06F9/30098 , G06F9/30145 , G06F9/3887 , G06F15/80 , G06T1/20
Abstract: An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.
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公开(公告)号：US11720328B2
公开(公告)日：2023-08-08
申请号：US17029836
申请日：2020-09-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Bin He , Shubh Shah , Michael Mantor
Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.
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公开(公告)号：US20230206543A1
公开(公告)日：2023-06-29
申请号：US17564160
申请日：2021-12-28
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Konstantin Igorevich SHKURKO , Michael Mantor
CPC classification number: G06T15/06 , G06T15/08 , G06T15/005 , G06T17/10 , G06T1/20 , G06F9/4881
Abstract: A processing unit employs a hardware traversal engine to traverse an acceleration structure such as a ray tracing structure. The hardware traversal engine includes one or more memory modules to store state information and other data used for the structure traversal, and control logic to execute a traversal process based on the stored data and based on received information indicating a source node of the acceleration structure to be used for the traversal process. By employing a hardware traversal engine, the processing unit is able to execute the traversal process more quickly and efficiently, conserving processing resources and improving overall processing efficiency.
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公开(公告)号：US11675568B2
公开(公告)日：2023-06-13
申请号：US17121354
申请日：2020-12-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Bin He , Brian Emberling , Mark Leather , Michael Mantor
CPC classification number: G06F7/57 , G06F9/3867 , G06F17/16 , G06T1/20 , G06F15/8015
Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.
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公开(公告)号：US11500778B2
公开(公告)日：2022-11-15
申请号：US16813075
申请日：2020-03-09
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan S. Jayasena , James Michael O'Connor , Michael Mantor
IPC: G06F12/0862 , G06F9/52 , G06F8/41
Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel with reduced intermediate state storage resource requirements. These include executing a prefetch kernel on a graphics processing unit (GPU), such that the prefetch kernel begins executing before a processing kernel. The prefetch kernel performs memory operations that are based upon at least a subset of memory operations in the processing kernel.
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公开(公告)号：US11295507B2
公开(公告)日：2022-04-05
申请号：US17091957
申请日：2020-11-06
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Leather , Michael Mantor
Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.
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40.发明申请
公开(公告)号：US20180121386A1
公开(公告)日：2018-05-03
申请号：US15354560
申请日：2016-11-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Angel E. Socarras , Michael Mantor , YunXiao Zou , Bin He
IPC: G06F15/80 , G06F9/30 , G06F12/0875 , G06F12/0891
CPC classification number: G06F15/8007 , G06F9/3001 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/3828 , G06F9/3851 , G06F9/3887 , G06F9/3891 , G06F12/0875 , G06F12/0891 , G06F2212/604
Abstract: A super single instruction, multiple data (SIMD) computing structure and a method of executing instructions in the super-SIMD is disclosed. The super-SIMD structure is capable of executing more than one instruction from a single or multiple thread and includes a plurality of vector general purpose registers (VGPRs), a first arithmetic logic unit (ALU), the first ALU coupled to the plurality of VGPRs, a second ALU, the second ALU coupled to the plurality of VGPRs, and a destination cache (Do$) that is coupled via bypass and forwarding logic to the first ALU, the second ALU and receiving an output of the first ALU and the second ALU. The Do$ holds multiple instructions results to extend an operand by-pass network to save read and write transactions power. A compute unit (CU) and a small CU including a plurality of super-SIMDs are also disclosed.
