Method of fabricating a gallium nitride p-i-n diode using implantation
    31.
    发明申请
    Method of fabricating a gallium nitride p-i-n diode using implantation 有权
    使用注入制造氮化镓p-i-n二极管的方法

    公开(公告)号:US20140346527A1

    公开(公告)日:2014-11-27

    申请号:US14454524

    申请日:2014-08-07

    Applicant: Avogy, Inc.

    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

    Abstract translation: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

    METHOD AND SYSTEM FOR GALLIUM NITRIDE VERTICAL JFET WITH SEPARATED GATE AND SOURCE
    32.
    发明申请
    METHOD AND SYSTEM FOR GALLIUM NITRIDE VERTICAL JFET WITH SEPARATED GATE AND SOURCE 审中-公开
    具有隔离栅和源的氮化钛垂直栅极的方法和系统

    公开(公告)号:US20140145201A1

    公开(公告)日:2014-05-29

    申请号:US13689574

    申请日:2012-11-29

    Applicant: AVOGY, INC.

    CPC classification number: H01L29/2003 H01L29/66446 H01L29/8083

    Abstract: A semiconductor structure includes a III-nitride substrate and a first III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The semiconductor structure also includes a first III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial layer and a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure. The semiconductor structure further includes a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial structure. The second III-nitride epitaxial layer is of a second conductivity type and is not electrically connected to the second III-nitride epitaxial structure.

    Abstract translation: 半导体结构包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的第一III族氮化物外延层。 半导体结构还包括耦合到第一III族氮化物外延层的第一导电类型的第一III族氮化物外延结构和耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构。 半导体结构还包括耦合到第一III族氮化物外延结构的第二III族氮化物外延层。 第二III族氮化物外延层是第二导电类型并且不与第二III族氮化物外延结构电连接。

    METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION
    35.
    发明申请
    METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION 有权
    使用植入制备GAN P-I-N二极体的方法

    公开(公告)号:US20150364612A1

    公开(公告)日:2015-12-17

    申请号:US14834306

    申请日:2015-08-24

    Applicant: Avogy, Inc.

    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

    Abstract translation: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

    Method and system for a gallium nitride vertical transistor
    36.
    发明授权
    Method and system for a gallium nitride vertical transistor 有权
    氮化镓垂直晶体管的方法和系统

    公开(公告)号:US09059199B2

    公开(公告)日:2015-06-16

    申请号:US13735912

    申请日:2013-01-07

    Applicant: AVOGY, Inc.

    Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

    Abstract translation: 垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。 远端外延层包括源通道的第一部分,并且相邻的图案化外延层被具有预定距离的间隙分开。 垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。 近端再生长的外延层包括源通道的第二部分。 垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触,与远端再生长的外延层电接触的栅极接触,以及与GaN衬底电接触的漏极接触 。

    GaN vertical superjunction device structures and fabrication methods
    37.
    发明授权
    GaN vertical superjunction device structures and fabrication methods 有权
    GaN垂直超导装置结构及制造方法

    公开(公告)号:US09029210B2

    公开(公告)日:2015-05-12

    申请号:US14302270

    申请日:2014-06-11

    Applicant: AVOGY, INC.

    Abstract: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    Abstract translation: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS
    38.
    发明申请
    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS 有权
    GAN垂直超导装置结构和制造方法

    公开(公告)号:US20140295652A1

    公开(公告)日:2014-10-02

    申请号:US14302270

    申请日:2014-06-11

    Applicant: AVOGY, INC.

    Abstract: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    Abstract translation: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    METHOD OF FABRICATING A GALLIUM NITRIDE MERGED P-I-N SCHOTTKY (MPS) DIODE
    39.
    发明申请
    METHOD OF FABRICATING A GALLIUM NITRIDE MERGED P-I-N SCHOTTKY (MPS) DIODE 有权
    氮化镓合并P-I-N肖特基(MPS)二极体的制备方法

    公开(公告)号:US20140287570A1

    公开(公告)日:2014-09-25

    申请号:US14299773

    申请日:2014-06-09

    Applicant: Avogy, Inc.

    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.

    Abstract translation: 半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。 半导体结构还包括III族氮化物外延结构,其包括耦合到III族氮化物衬底的第一侧的第一III族氮化物外延层和多个第二导电类型的III族氮化物区域。 多个III族氮化物区域在多个III族氮化物区域中的每一个之间具有至少一个第一导电类型的III族氮化物外延区域。 半导体结构还包括电耦合到多个III族氮化物区域和至少一个III族氮化物外延区域中的一个或多个的第一金属结构。 在第一金属结构和至少一个III族氮化物外延区之间产生肖特基接触。

    METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION
    40.
    发明申请
    METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION 有权
    使用电导率调制的燃料材料中结点终止的方法和系统

    公开(公告)号:US20140206179A1

    公开(公告)日:2014-07-24

    申请号:US14220564

    申请日:2014-03-20

    Applicant: AVOGY, INC.

    Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.

    Abstract translation: 半导体结构包括具有第一表面和与第一表面相对的第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 半导体结构还包括耦合到GaN衬底的第二表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN外延层。 第二GaN外延层包括有源器件区,第一结端接区,其特征在于具有第一注入分布的注入区,以及第二结终端区,其特征在于具有第二注入分布的注入区。

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