公开(公告)号：US06900074B2

公开(公告)日：2005-05-31

申请号：US10422942

申请日：2003-04-25

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L25/10 ,  H01L27/108 ,  H01L21/48 ,  H01L23/02

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

摘要翻译： 这里描述的是根据本发明的堆叠式封装，其中密封半导体芯片的多个带状载体在上下方向上多层叠。 在叠层封装中，形成在每个带载体的整个表面上的引线的一端电连接到其对应的半导体芯片的连接端子。 引线的另一端电连接到其在​​带载体中限定的相应的通孔。 在多个带状载体的相同位置形成有与多个半导体芯片共用的连接端子，并且通过多个相互贯穿的贯通孔将其连接到相同的外部连接端子。

公开(公告)号：US06785165B2

公开(公告)日：2004-08-31

申请号：US10309238

申请日：2002-12-04

申请人： Takayuki Kawahara ,  Nozomu Matsuzaki ,  Terumi Sawase ,  Masaharu Kubo

发明人： Takayuki Kawahara ,  Nozomu Matsuzaki ,  Terumi Sawase ,  Masaharu Kubo

IPC分类号： G11C1604

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7885

摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

公开(公告)号：US5670409A

公开(公告)日：1997-09-23

申请号：US511810

申请日：1995-08-07

申请人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

发明人： Hiroshi Otori ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Masaharu Kubo ,  Atsuyoshi Koike ,  Fumiyuki Kanai

IPC分类号： H01L21/304 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/1052

摘要： A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insulating film to suppress the level difference in the insulating film for enhancing a focus margin for successive photolithographic steps; and forming wiring conductors on the insulating film with the suppressed level difference, enjoying the enhanced focus margin.

摘要翻译： 一种制造半导体集成电路器件的方法包括：使半导体衬底的第二表面部分凹陷; 形成能够在半导体衬底的第一表面部分处执行第一功能的第一电路区域的元件和能够在半导体衬底的凹入的第二表面部分执行第二功能的第二电路区域的元件， 第一电路区域和第二电路区域的第一电路区域分别具有通常在垂直于半导体衬底的表面部分的方向上测量的相对较小和大的尺寸; 形成绝缘膜以覆盖第一和第二电路区域，结果是在第一和第二电路区域上的绝缘膜的第一和第二部分之间在相对较低的电平和相对较高的水平上产生电平差， 分别; 实现绝缘膜的化学机械平面化，以抑制绝缘膜中的水平差，以提高连续光刻步骤的聚焦余量; 并且在绝缘膜上形成具有抑制的电平差的布线导体，享受增强的聚焦余量。

公开(公告)号：US4956688A

公开(公告)日：1990-09-11

申请号：US374570

申请日：1989-06-27

申请人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L29/7327

摘要： A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有高抗免除由α射线引起的软误差的结构的双极记忆。 触发器的晶体管，即存储单元的基本电路被反转，并且其负载装置具有用于屏蔽触发器与基板内产生的噪声的屏蔽装置。 采用pnp型晶体管或肖特基势垒二极管作为负载器件。 在设置有器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层。 跨越掩埋层和掺杂层施加反向偏压，以切断衬底内产生的噪声。

公开(公告)号：US4858184A

公开(公告)日：1989-08-15

申请号：US42698

申请日：1987-04-27

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411

CPC分类号： G11C11/4113 ,  G11C11/4116

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

公开(公告)号：US4577231A

公开(公告)日：1986-03-18

申请号：US476415

申请日：1983-03-17

申请人： Shinya Ohba ,  Haruhisa Ando ,  Masaaki Nakai ,  Toshifumi Ozaki ,  Koichi Seki ,  Kenji Takahashi ,  Toshiyuki Akiyama ,  Iwao Takemoto ,  Takuya Imaide ,  Akihide Okuda ,  Masaharu Kubo

发明人： Shinya Ohba ,  Haruhisa Ando ,  Masaaki Nakai ,  Toshifumi Ozaki ,  Koichi Seki ,  Kenji Takahashi ,  Toshiyuki Akiyama ,  Iwao Takemoto ,  Takuya Imaide ,  Akihide Okuda ,  Masaharu Kubo

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/341 ,  H04N5/359 ,  H04N5/365 ,  H04N5/372 ,  H04N3/14

CPC分类号： H04N3/1512 ,  H01L27/14643

摘要： Disclosed is a two-dimensionally arrayed solid-state imaging device for a television camera having a photodiode array arranged at a photo-sensing section and a readout horizontal register constructed by a charge transfer device (CTD) such as a BCD, CCD or BBD. An inverter circuit is provided for each of the vertical signal lines. An input of the inverter circuit is connected to a vertical signal line drain of at least one transfer transistor arranged between the vertical signal line and the CTD, and an output of the inverter circuit is connected to a gate of the transfer transistor. Transfer efficiency is improved by the insertion of the inverter circuit and fixed pattern noise is substantially reduced by supplying bias currents.

摘要翻译： 公开了一种用于电视摄像机的二维阵列固态成像装置，其具有布置在感光部分的光电二极管阵列和由诸如BCD，CCD或BBD的电荷转移装置（CTD）构成的读出水平寄存器。 为每条垂直信号线提供一个反相器电路。 逆变器电路的输入端连接在布置在垂直信号线和CTD之间的至少一个传输晶体管的垂直信号线漏极，反相器电路的输出端连接到转移晶体管的栅极。 通过插入逆变器电路来提高转移效率，并且通过提供偏置电流大大减少固定图案噪声。

公开(公告)号：US4349743A

公开(公告)日：1982-09-14

申请号：US206865

申请日：1980-11-14

申请人： Shinya Ohba ,  Shoji Hanamura ,  Toshifumi Ozaki ,  Masaharu Kubo ,  Masaaki Nakai ,  Kenji Takahashi ,  Masakazu Aoki ,  Iwao Takemoto ,  Haruhisa Ando ,  Ryuichi Izawa

发明人： Shinya Ohba ,  Shoji Hanamura ,  Toshifumi Ozaki ,  Masaharu Kubo ,  Masaaki Nakai ,  Kenji Takahashi ,  Masakazu Aoki ,  Iwao Takemoto ,  Haruhisa Ando ,  Ryuichi Izawa

IPC分类号： H01L27/14 ,  H01L27/146 ,  H04N3/14 ,  H04N5/335 ,  H04N5/341 ,  H04N5/359 ,  H04N5/365 ,  H04N5/372 ,  H04N5/374 ,  H04N5/378

CPC分类号： H01L27/14643 ,  H04N3/1512 ,  H04N3/1568

摘要： A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.

摘要翻译： 一种固态成像装置，其中MOS传感器用于光电传感器部分，CTD移位寄存器用于读出电路，第一和第二传输门连接在垂直信号输出线和CTD之间，复位门 连接在第一和第二传输门的接合点与复位电压线之间。 采用在水平消隐期间将多行的信号输出传送到CTD的方法，并且在水平扫描期间同时读出多行的信号。 在信号传输中，偏置电荷从CTD倾倒到垂直信号输出线路中，由偏置电荷和信号电荷组成的混合电荷转移到CTD。 此后，读出信号。

公开(公告)号：US4295055A

公开(公告)日：1981-10-13

申请号：US46028

申请日：1979-06-06

申请人： Iwao Takemoto ,  Norio Koike ,  Shinya Ohba ,  Haruhisa Ando ,  Masaaki Nakai ,  Syoji Hanamura ,  Ryuichi Izawa ,  Masaharu Kubo ,  Masakazu Aoki ,  Shuhei Tanaka

发明人： Iwao Takemoto ,  Norio Koike ,  Shinya Ohba ,  Haruhisa Ando ,  Masaaki Nakai ,  Syoji Hanamura ,  Ryuichi Izawa ,  Masaharu Kubo ,  Masakazu Aoki ,  Shuhei Tanaka

IPC分类号： G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H01L27/146 ,  H01L31/10 ,  H03K5/15 ,  H04N3/14

CPC分类号： H03K5/15093 ,  G11C19/184 ,  G11C19/28

摘要： A circuit for generating scanning pulses comprising a plurality of stages of basic circuits connected in series, said each basic circuit comprising first, second and third insulated gate field-effect transistors (MISTs) each of which has first and second terminals each being either of source and drain terminals and a gate terminal, said first terminal of said first MIST being used as a clock pulse-applying terminal, said gate terminal of said first MIST being used as an input terminal, said second terminal of said first MIST and said first terminal and said gate terminal of said second MIST being connected and used as a scanning pulse output terminal, said second terminal of said second MIST and said first terminal of said third MIST being connected and used as an output terminal, said second terminal of said third MIST being used as a ground terminal, said gate terminal of said third MIST being used as a feedback input terminal.

摘要翻译： 一种用于产生扫描脉冲的电路，包括串联连接的多级基本电路，所述每个基本电路包括第一，第二和第三绝缘栅极场效应晶体管（MIST），每个绝缘栅场效应晶体管的第一和第二端子均为源极 所述第一MIST的所述第一端子用作时钟脉冲施加端子，所述第一MIST的所述栅极端子用作输入端子，所述第一MIST的所述第二端子和所述第一端子的所述第一端子 并且所述第二MIST的所述栅极端子被连接并用作扫描脉冲输出端子，所述第二MIST的所述第二端子和所述第三MIST的所述第一端子被连接并用作输出端子，所述第三MIST的所述第二端子 被用作接地端子，所述第三MIST的所述栅极端子用作反馈输入端子。

公开(公告)号：US4280065A

公开(公告)日：1981-07-21

申请号：US969269

申请日：1978-12-14

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K19/082 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K3/01 ,  H03K19/08

CPC分类号： H03K19/09429 ,  H03K19/0823 ,  H03K19/09448 ,  H03K5/023

摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).

摘要翻译： 本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个 。 三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑 电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。 外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。

公开(公告)号：US4267469A

公开(公告)日：1981-05-12

申请号：US066880

申请日：1979-08-16

申请人： Shinya Ohba ,  Iwao Takemoto ,  Masaaki Nakai ,  Haruhisa Ando ,  Masaharu Kubo

发明人： Shinya Ohba ,  Iwao Takemoto ,  Masaaki Nakai ,  Haruhisa Ando ,  Masaharu Kubo

IPC分类号： H01L27/146 ,  H03K3/42 ,  H01L27/14 ,  H01L29/78 ,  H01L31/00

CPC分类号： H04N5/335 ,  H01L27/14654 ,  H04N5/3591

摘要： In a solid-state imaging device having on an identical semiconductor substrate a plurality of photodiodes which are arrayed in two dimensions, vertical and horizontal switching MOSFETs which select the positions of the photodiodes, and vertical and horizontal scanning circuits which provide scanning pulses for controlling the operations of the vertical and horizontal switching MOSFETs; the improvement therein comprising a clamping circuit which is made up of a diode, a MOSFET or the like and which is disposed between the photodiode and a vertical scanning line of the succeeding stage, so that excess charges overflowing the photodiode are drawn out from the vertical scanning line through the clamping circuit, whereby the blooming can be prevented.

摘要翻译： 在具有相同半导体衬底的固态成像器件中，排列有二维排列的多个光电二极管，选择光电二极管的位置的垂直和水平开关MOSFET以及提供扫描脉冲的垂直和水平扫描电路，用于控制 垂直和水平开关MOSFET的工作; 其改进在于包括由二极管，MOSFET等组成并且设置在光电二极管和后级的垂直扫描线之间的钳位电路，使得溢出光电二极管的过量电荷从垂直线 扫描线通过钳位电路，从而可以防止起霜。