公开(公告)号：US20050111255A1

公开(公告)日：2005-05-26

申请号：US10721184

申请日：2003-11-26

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C11/404 ,  H01L27/108 ,  G11C11/34

CPC分类号： H01L27/108 ,  G11C11/404

摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

摘要翻译： 实施例涉及浮体动态随机存取存储器（FBDRAM）。 在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

公开(公告)号：US20060285393A1

公开(公告)日：2006-12-21

申请号：US11158518

申请日：2005-06-21

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

IPC分类号： G11C16/04

CPC分类号： G11C17/18

摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

摘要翻译： 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

公开(公告)号：US20060279985A1

公开(公告)日：2006-12-14

申请号：US11151982

申请日：2005-06-14

申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C2211/4016

摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

摘要翻译： 通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。 每个存储单元包括具有能够存储电荷的浮动体的晶体管。 多个字线和清除线与存储器单元的行互连。 多个位线被连接到存储器单元的列。 通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

公开(公告)号：US20060092742A1

公开(公告)日：2006-05-04

申请号：US10979605

申请日：2004-11-01

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC分类号： G11C17/18

CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

摘要： Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

摘要翻译： 本公开中提供了一次性可编程反熔丝电池的不同实施例。 在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。 反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。 感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。 高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

公开(公告)号：US20060054977A1

公开(公告)日：2006-03-16

申请号：US10942019

申请日：2004-09-16

申请人： Dinesh Somasekhar ,  Shekhar Borkar ,  Vivek De ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu

发明人： Dinesh Somasekhar ,  Shekhar Borkar ,  Vivek De ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C11/404 ,  G11C16/0416

摘要： A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may be formed on each of the floating gates of memory cells forming the column of the plurality of memory cells. The coupling bit-line may also be formed within a well of each of memory cells forming the column of the plurality of memory cells.

摘要翻译： 提供一种存储器件，其包括多个存储器单元，其中每个存储器单元包括源极区域，漏极区域和浮动栅极。 还提供了在多个存储单元中的至少一列延伸的耦合位线。 耦合位线可以形成在形成多个存储单元的列的存储单元的每个浮置栅极上。 耦合位线也可以形成在形成多个存储器单元的列的每个存储单元的阱中。

公开(公告)号：US20050145886A1

公开(公告)日：2005-07-07

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

发明人： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C11/404 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

摘要翻译： 一些实施例提供了包括体区，源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。

公开(公告)号：US20050135169A1

公开(公告)日：2005-06-23

申请号：US10740551

申请日：2003-12-22

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad Khellah ,  Fabrice Paillet ,  Stephen Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek De

IPC分类号： G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C7/02

CPC分类号： G11C11/4099 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097

摘要： An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

摘要翻译： 公开了一种用于在存储器电路中产生参考的装置和方法。 使用至少两个伪位单元来产生参考电压。 一个单元格具有高存储值，另一个存储值较低。 电池被激活并放电到相应的位线。 在放电过程期间，位线被均衡以产生大约高值单元和低值单元之间的中点的参考。

公开(公告)号：US20070076463A1

公开(公告)日：2007-04-05

申请号：US11239903

申请日：2005-09-30

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

摘要： According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

摘要翻译： 根据本发明的实施例，一次可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 在实施例中，存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则跨越存取晶体管的栅极/漏极结的电压不足以导致 栅极氧化层的存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

公开(公告)号：US20060291265A1

公开(公告)日：2006-12-28

申请号：US11169106

申请日：2005-06-27

申请人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

发明人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

IPC分类号： G11C17/00

CPC分类号： G11C17/18

摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

摘要翻译： 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

公开(公告)号：US07031203B2

公开(公告)日：2006-04-18

申请号：US11066395

申请日：2005-02-28

申请人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

发明人： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

IPC分类号： G11C5/14

CPC分类号： H01L27/108 ,  G11C11/404 ,  G11C11/4085 ,  H01L29/7841

摘要： A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.

摘要翻译： DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。 晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。 晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。 通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。