Slow Speed Mute Resistance Via Selective COFDM Bin Loading
    31.
    发明申请
    Slow Speed Mute Resistance Via Selective COFDM Bin Loading 失效
    通过选择性COFDM箱装载的慢速静音电阻

    公开(公告)号:US20090245087A1

    公开(公告)日:2009-10-01

    申请号:US12415648

    申请日:2009-03-31

    Abstract: Systems and methods are presented for improving the ability to withstand slow speed mute via diversity transmission while avoiding loss in link level margin. In exemplary embodiments of the present invention, systems and methods are presented for improving resistance to slow speed muting by employing transmit diversity where a second signal is not a replica of the original signal. The second signal can be generated, for example, by using only a COFDM FFT bin that contained the cluster sync bit while setting all other bins to zero. That is, only the spectral portion of interest of the COFDM signal need be utilized. In such exemplary embodiments, the same frequency and time delay offset can be used as in current systems and methods, except that the replica COFDM signal can, for example, consist of only one populated FFT bin.

    Abstract translation: 提出了系统和方法,以提高通过分集传输来承受慢速静音的能力,同时避免链路水平裕度的损失。 在本发明的示例性实施例中,提出了用于通过采用发射分集来提高对慢速静音的抵抗力的系统和方法,其中第二信号不是原始信号的复制品。 例如,可以通过仅使用包含集群同步位的COFDM FFT仓而将所有其他箱设置为零来生成第二信号。 也就是说,仅需要利用COFDM信号的感兴趣的频谱部分。 在这样的示例性实施例中,可以使用与当前系统和方法相同的频率和时间延迟偏移,除了复制COFDM信号可以例如仅由一个填充的FFT仓组成。

    Methods and apparatus for interoperable satellite radio receivers
    32.
    发明申请
    Methods and apparatus for interoperable satellite radio receivers 有权
    可互操作卫星无线电接收机的方法和装置

    公开(公告)号:US20080311845A1

    公开(公告)日:2008-12-18

    申请号:US12080135

    申请日:2008-03-31

    CPC classification number: H04B7/18513

    Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals, such as, for example, one signal from XM Satellite Radio, the other signal from Sirius Satellite Radio. The methods and apparatus presented utilize common receiver functions to process each signal, thereby obviating the need to duplicate hardware elements. In exemplary embodiments of the present invention, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

    Abstract translation: 提出了一种方法和装置,以允许一个接收器架构用于接收两个不同的SDARS信号,例如来自XMS卫星无线电的一个信号,来自Sirius卫星广播的另一个信号。 所提出的方法和装置利用公共接收机功能来处理每个信号,从而避免复制硬件元件的需要。 在本发明的示例性实施例中,可以假设两个信号将不被同时接收,从而允许相当大的硬件重用并降低可互操作的接收机的成本。 要强调的是,该摘要被提供以符合要求摘要的规则,这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Efficient implementation to perform iterative decoding with large iteration counts
    33.
    发明申请
    Efficient implementation to perform iterative decoding with large iteration counts 失效
    高效实现以大的迭代计数执行迭代解码

    公开(公告)号:US20080307294A1

    公开(公告)日:2008-12-11

    申请号:US12079467

    申请日:2008-03-26

    CPC classification number: H03M13/6505 H03M13/05 H03M13/1105 H03M13/3746

    Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, and is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

    Abstract translation: 提出了系统和方法,以通过提供弹性缓冲来提高恒定比特率迭代解码器的性能,同时利用能够维持较低值的固定次数迭代的相对简单的解码器架构。 例如,LDPC解码器可以被设计为支持小于最大可能的迭代次数,并且可以例如与弹性输入和输出缓冲器配合。 如果给定代码块或连续的代码块需要用于解码的最大迭代次数,则解码器可以例如以这样的最大迭代次数运行,并且弹性输入缓冲器可以例如保持等待 进行处理以保持恒定的输入速率。 或者,如果一个或多个代码块需要小于标称的迭代次数,则输出缓冲器可以存储那些代码块,以便保持恒定的输出速率。 要强调的是,提供本摘要以符合要求抽象的规则,并提交了一项谅解,即不会将其用于解释或限制权利要求书的范围或含义。

    Systems and methods for antenna diversity combining for satellite radio signals
    34.
    发明申请
    Systems and methods for antenna diversity combining for satellite radio signals 失效
    用于卫星无线电信号的天线分集的系统和方法

    公开(公告)号:US20070142009A1

    公开(公告)日:2007-06-21

    申请号:US11607383

    申请日:2006-12-01

    CPC classification number: H04B7/0871 H04B7/0868

    Abstract: Systems and methods are presented for digital antenna diversity combining. In exemplary embodiments of the present invention, at least two antenna signal paths can be communicably connected to a receiver. Each antenna signal path can be provided with an RF tuner communicably connected to a demodulator, which can estimate the signal to noise ratio (SNR) and time of arrival of its respective antenna signal. In exemplary embodiments of the present invention, a time alignment circuit can be communicably connected to each antenna signal path, and a maximum ratio combiner can be communicably connected to the time alignment circuit. In operation, the time alignment circuit can use the time of arrival estimate to align the multiple signals and the maximum ratio combiner can use the SNR estimate obtained for each antenna signal to respectively weight each signal and thereby generate a combined output signal. In exemplary embodiments of the present invention, a switch diversity combiner can be further provided, and can quickly detect when an antenna signal is entering a fade, allowing the maximum ratio combiner to set that signal's weight to zero. In exemplary embodiments of the present invention, a digital diversity combiner can be provided in a stand alone integrated circuit, or can be integrated in a larger integrated circuit, such as, for example, a satellite radio overlay processor.

    Abstract translation: 提出了数字天线分集组合的系统和方法。 在本发明的示例性实施例中,至少两个天线信号路径可以可通信地连接到接收器。 每个天线信号路径可以设置有可通信地连接到解调器的RF调谐器,其可以估计其相应天线信号的信噪比(SNR)和到达时间。 在本发明的示例性实施例中,时间对准电路可以可通信地连接到每个天线信号路径,并且最大比率组合器可以可通信地连接到时间对准电路。 在操作中,时间对准电路可以使用到达时间估计来对准多个信号,并且最大比组合器可以使用为每个天线信号获得的SNR估计来分别对每个信号加权,从而生成组合的输出信号。 在本发明的示例性实施例中,可以进一步提供开关分集组合器,并且可以快速检测何时天线信号进入衰落,允许最大比组合器将该信号的权重设置为零。 在本发明的示例性实施例中,数字分集组合器可以设置在独立集成电路中,或者可以集成在诸如卫星无线电覆盖处理器之类的较大集成电路中。

Patent Agency Ranking