Managing memory faults
    31.
    发明授权
    Managing memory faults 有权
    管理内存故障

    公开(公告)号:US08386836B2

    公开(公告)日:2013-02-26

    申请号:US13465602

    申请日:2012-05-07

    IPC分类号: G06F11/00

    摘要: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.

    摘要翻译: 描述了用于管理存储器故障的实施例。 示例系统可以包括用于管理存储器单元并报告存储器故障的存储器控​​制器模块。 错误缓冲器模块可以存储从存储器控制器接收到的存储器故障信息。 通知模块可以与错误缓冲模块通信。 通知模块可以在存储器访问操作中生成存储器故障的通知。 系统软件模块可以在处理器上提供服务和管理执行程序。 此外,系统软件模块可以接收内存访问操作的内存故障通知。 当接收到存储器访问操作中的存储器故障的通知时,通知处理程序可能被中断激活。

    Control-flow prediction using multiple independent predictors
    33.
    发明授权
    Control-flow prediction using multiple independent predictors 有权
    使用多个独立预测因子的控制流预测

    公开(公告)号:US08127119B2

    公开(公告)日:2012-02-28

    申请号:US12329517

    申请日:2008-12-05

    CPC分类号: G06F9/3885 G06F9/3848

    摘要: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.

    摘要翻译: 本公开通常描述具有包括一个或多个分支预测器布置的多核处理器的计算系统。 分支预测器被配置为预测与其相关联的并且将在计算系统的至少一个处理器核心上执行的单个和完整的程序指令流。 通过描述的方法可以改善整体处理器性能和物理可扩展性。

    MANAGING MEMORY FAULTS
    34.
    发明申请
    MANAGING MEMORY FAULTS 有权
    管理存储器故障

    公开(公告)号:US20110283135A1

    公开(公告)日:2011-11-17

    申请号:US12780931

    申请日:2010-05-17

    IPC分类号: G06F11/20 G06F11/07 G06F11/00

    摘要: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.

    摘要翻译: 描述了用于管理存储器故障的实施例。 示例系统可以包括用于管理存储器单元并报告存储器故障的存储器控​​制器模块。 错误缓冲器模块可以存储从存储器控制器接收到的存储器故障信息。 通知模块可以与错误缓冲模块通信。 通知模块可以在存储器访问操作中生成存储器故障的通知。 系统软件模块可以在处理器上提供服务和管理执行程序。 此外,系统软件模块可以接收内存访问操作的内存故障通知。 当接收到存储器访问操作中的存储器故障的通知时,通知处理程序可能被中断激活。

    BURST-BASED CACHE DEAD BLOCK PREDICTION
    35.
    发明申请
    BURST-BASED CACHE DEAD BLOCK PREDICTION 有权
    基于BURST的缓存死锁预测

    公开(公告)号:US20110087845A1

    公开(公告)日:2011-04-14

    申请号:US12579183

    申请日:2009-10-14

    IPC分类号: G06F12/08 G06F12/00

    CPC分类号: G06F12/0879

    摘要: The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage locations for a first cache block, with a most recently used position location in the cache memory. A cache controller may be configured to predict whether the first cache block stored in the cache memory is identified as a dead cache block based on a cache burst of the first cache block. The cache burst may comprise a first access of the first cache block by a cache client and any subsequent contiguous accesses of the first cache block following the first access by the cache client while the first cache block is in a most recently used position of the cache set.

    摘要翻译: 本公开通常涉及用于识别高速缓冲存储器系统中的死缓存块的高速缓存存储器系统和/或技术。 示例系统可以包括可由缓存客户端访问的高速缓存存储器。 高速缓冲存储器可以包括用于第一高速缓存块的多个存储位置,其中最近使用的位置位置在高速缓冲存储器中。 高速缓存控制器可以被配置为基于第一高速缓存块的高速缓存突发来预测存储在高速缓冲存储器中的第一高速缓存块是否被识别为死区高速缓存块。 高速缓存突发可以包括由高速缓存客户端进行的第一高速缓存块的第一次访问以及第一高速缓存块处于高速缓存的最近使用位置之后由缓存客户机进行第一次访问之后的第一高速缓存块的任何后续连续访问 组。