利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

134 条记录 (耗时 0.053 秒)

    Programmable transceivers that are able to operate over wide frequency ranges
    31.
    发明授权
    Programmable transceivers that are able to operate over wide frequency ranges 有权
    能够在宽频率范围内工作的可编程收发器

    公开(公告)号：US07539278B2

    公开(公告)日：2009-05-26

    申请号：US11292565

    申请日：2005-12-02

    申请人： Sergey Yuryevich Shumarayev ,  Rakesh Patel

    发明人： Sergey Yuryevich Shumarayev ,  Rakesh Patel

    IPC分类号： H03D3/24

    CPC分类号： H03K19/17744 ,  H03L7/0995

    摘要： A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

    摘要翻译： 现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或 数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

    Programmable logic device serial interface having dual-use phase-locked loop circuitry
    38.
    发明授权
    Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
    具有双用途锁相环电路的可编程逻辑器件串行接口

    公开(公告)号：US06867616B1

    公开(公告)日：2005-03-15

    申请号：US10455773

    申请日：2003-06-04

    申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

    发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

    IPC分类号： H03K19/177 ,  H03K19/173 ,  H03D3/24

    CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

    摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.

    摘要翻译： 在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。 这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。 对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

    Interconnection resources for programmable logic integrated circuit devices
    39.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06366120B1

    公开(公告)日：2002-04-02

    申请号：US09517146

    申请日：2000-03-02

    申请人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    发明人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC分类号： H03K190177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    High performance output buffer
    40.
    发明授权
    High performance output buffer 有权
    高性能输出缓冲器

    公开(公告)号：US6154059A

    公开(公告)日：2000-11-28

    申请号：US199705

    申请日：1998-11-24

    申请人： Sammy Cheung ,  John Lam ,  Rakesh Patel ,  Tony Ngai

    发明人： Sammy Cheung ,  John Lam ,  Rakesh Patel ,  Tony Ngai

    IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/094

    CPC分类号： H03K19/00361

    摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.

    摘要翻译： 输出缓冲器具有连接在输入节点和输出节点之间的内部电路。 内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。 嘈杂的电源电压处于高于静态电源的电压电平。 第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。 第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组 一组晶体管。 输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。