公开(公告)号：US06809029B2

公开(公告)日：2004-10-26

申请号：US10149858

申请日：2002-10-07

申请人： Takeshi Nogami ,  Naoki Komai

发明人： Takeshi Nogami ,  Naoki Komai

IPC分类号： H01L214763

CPC分类号： H01L21/67167 ,  B24B37/04 ,  C25D7/123 ,  C25D17/001 ,  H01L21/67219 ,  H01L21/6723

摘要： The present invention provides a semiconductor manufacturing apparatus capable of shortening TAT by completing a plurality of processes including plating, annealing, and CMP-in-twice or the like in copper wiring process in a single manufacturing apparatus, and is also capable of suppressing costs for consumable materials by replacing the CMP step with other step. The apparatus of the present invention comprises an electrolytic plating chamber (11) for performing electrolytic plating of a substrate (91), an electrolytic polishing chamber (21) for performing electrolytic polishing of the substrate, and a conveying chamber (81) having installed therein a conveying instrument (83) responsible for loading/unloading of the substrate to or from the electrolytic plating chamber, and to or from he electrolytic polishing chamber, and is connected respectively to the electrolytic plating chamber and the electrolytic polishing chamber. The conveying chamber may further have connected thereto an electroless plating chamber, an annealing chamber, a liquid treatment chamber or the like.

摘要翻译： 本发明提供一种半导体制造装置，其能够通过在单个制造装置中的铜布线工序中完成包括电镀，退火和CMP二次等的多个处理来缩短TAT，并且还能够抑制成本 通过用其他步骤代替CMP步骤来消耗材料。 本发明的装置包括用于进行基板（91）的电解电镀的电解电镀室（11），用于对基板进行电解抛光的电解抛光室（21），以及安装在其中的输送室 负责将基板装载到电解电镀室和从电解电镀室进行加载/卸载的输送装置（83），并且分别与电解电镀室和电解研磨室连接。 输送室还可以连接有无电镀室，退火室，液体处理室等。

公开(公告)号：US06797623B2

公开(公告)日：2004-09-28

申请号：US09800580

申请日：2001-03-08

申请人： Shuzo Sato ,  Yuji Segawa ,  Akira Yoshio ,  Hiizu Ootorii ,  Zenya Yasuda ,  Masao Ishihara ,  Takeshi Nogami ,  Naoki Komai

发明人： Shuzo Sato ,  Yuji Segawa ,  Akira Yoshio ,  Hiizu Ootorii ,  Zenya Yasuda ,  Masao Ishihara ,  Takeshi Nogami ,  Naoki Komai

IPC分类号： H01L21302

CPC分类号： B24B37/042 ,  B23H5/08 ,  B24B37/046 ,  B24B37/16 ,  B24B37/26 ,  C25F3/30 ,  C25F7/00 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843

摘要： A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper film is flattened.

摘要翻译： 一种生产方法和抛光半导体器件和抛光装置的方法，其能够容易地平坦化金属膜的初始不均匀性，除去过量金属膜的效率优异，并且能够抑制对层间绝缘膜的损伤 在通过抛光使金属膜平坦化时，金属膜下方的抛光方法包括以下步骤：在阴极构件和铜膜之间插入包含螯合剂的电解液，在用作阴极的阴极构件和铜 膜用作氧化铜膜的表面并形成氧化铜的螯合膜，选择性地除去与铜膜形状相对应的螯合膜的突出部分，以暴露铜膜的突出部分 并重复上述螯合膜形成步骤和上述螯合膜去除步骤，直到突出 使铜膜变平。

公开(公告)号：US06563222B1

公开(公告)日：2003-05-13

申请号：US09999703

申请日：2001-10-24

申请人： Takeshi Nogami ,  Sergey Lopatin

发明人： Takeshi Nogami ,  Sergey Lopatin

IPC分类号： H01L2348

CPC分类号： H01L21/76877 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.

摘要翻译： 一种用于制造半导体芯片的方法包括：经由沟道邻近布置铜互连，然后仅掺杂直接位于通孔通道下方的互连部分。 然后，通孔通道填充有导电材料。 局部掺杂互连的杂质减少了互连通孔界面处铜原子的不必要的电迁移，同时不会过度增加互连中的线电阻。

公开(公告)号：US06368961B1

公开(公告)日：2002-04-09

申请号：US09723812

申请日：2000-11-28

申请人： Sergey D. Lopatin ,  Takeshi Nogami

发明人： Sergey D. Lopatin ,  Takeshi Nogami

IPC分类号： H01L2124

CPC分类号： H01L21/76871 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate a tungsten nitride barrier layer. The high concentration of nitrogen in the copper alloy provides good adhesion of the seed layer to the barrier layer while the lack of nitrogen away from the barrier layer allows the copper conductive to have good adhesion with the pure copper conductive material.

摘要翻译： 提供了一种形成半导体铜种子层的方法，其中铜与由锡，镁和铝组成的组中的一种合金化。 该合金还具有氮化氮阻挡层附近氮浓度最高的氮。 铜合金中的高浓度氮提供了种子层与阻挡层的良好粘附性，而阻挡层的氮缺乏使得铜导电体与纯铜导电材料具有良好的粘合性。

公开(公告)号：US06214731B1

公开(公告)日：2001-04-10

申请号：US09442771

申请日：1999-11-18

申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

公开(公告)号：US06172421B2

公开(公告)日：2001-01-09

申请号：US09132282

申请日：1998-08-11

申请人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

发明人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

IPC分类号： H01L2348

CPC分类号： H01L21/76858 ,  H01L21/76849 ,  H01L21/76886

摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

摘要翻译： 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

公开(公告)号：US6165894A

公开(公告)日：2000-12-26

申请号：US131872

申请日：1998-08-10

申请人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

发明人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76886 ,  H01L21/76834 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.

摘要翻译： 通过用氨等离子体处理Cu或Cu合金互连构件的暴露表面，然后在经处理的表面上沉积扩散阻挡层，扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附性显着增强。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，用氨等离子体处理Cu / Cu合金互连的暴露表面，并直接沉积氮化硅扩散阻挡层 在等离子体处理的表面上。

公开(公告)号：US6147000A

公开(公告)日：2000-11-14

申请号：US225546

申请日：1999-01-05

申请人： Lu You ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Lu You ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76886 ,  H01L21/76849 ,  H01L21/76858

摘要： A Cu interconnect member is passivated by diffusing Sn, Ta or Cr atoms into its upper surface to form an intermetallic layer. Embodiments include depositing Cu by electroplating or electroless plating to fill a damascene opening in a dielectric layer, CMP, depositing a sacrificial layer of Sn, Ta or Cr on the planarized surface, heating to diffuse Sn, Ta or Cr into the upper surface of the deposited Cu to form a passivating intermetallic alloy layer, and removing any remaining sacrificial layer by CMP or etching.

摘要翻译： 通过将Sn，Ta或Cr原子扩散到其上表面来形成金属间化合物来钝化Cu互连构件。 实施例包括通过电镀或化学电镀沉积Cu以填充电介质层中的镶嵌开口，CMP，在平坦化表面上沉积Sn，Ta或Cr的牺牲层，加热以将Sn，Ta或Cr扩散到 沉积Cu以形成钝化金属间合金层，并通过CMP或蚀刻去除任何残留的牺牲层。

公开(公告)号：US6103624A

公开(公告)日：2000-08-15

申请号：US293559

申请日：1999-04-15

申请人： Takeshi Nogami ,  Dirk D. Brown ,  Sergey Lopatin

发明人： Takeshi Nogami ,  Dirk D. Brown ,  Sergey Lopatin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/441 ,  H01L21/428 ,  H01L21/445 ,  H01L21/447

CPC分类号： H01L23/53238 ,  H01L21/76838 ,  H01L21/76877 ,  H01L2924/0002

摘要： Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.

摘要翻译： 具有铜互连的半导体器件，其中阻挡金属层被施加在具有多个沟槽的电介质层的表面上。 阻挡层金属层对沟槽进行排列。 将铜层放置在阻挡金属层上方并填充沟槽。 不在沟槽内部的铜层的部分被抛光，确保阻挡金属层不被抛光。 铜层被激光退火以增加晶粒尺寸，去除接缝，并且在阻挡金属层和铜层之间提供更好的界面结合。 阻挡金属层在退火过程中保护介电层。 通过抛光除去不在沟槽中的阻挡金属层的一部分。

公开(公告)号：US09245794B2

公开(公告)日：2016-01-26

申请号：US13614492

申请日：2012-09-13

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

摘要翻译： 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。