公开(公告)号：US07457183B2

公开(公告)日：2008-11-25

申请号：US11580995

申请日：2006-10-16

申请人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen ,  Eduardo Maayan

发明人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen ,  Eduardo Maayan

IPC分类号： G11C7/02

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5634

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

摘要翻译： 一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位 相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。 与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

公开(公告)号：US20060018153A1

公开(公告)日：2006-01-26

申请号：US11194394

申请日：2005-08-01

申请人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen

发明人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen

IPC分类号： G11C16/04

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5634

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

公开(公告)号：US07668017B2

公开(公告)日：2010-02-23

申请号：US11205716

申请日：2005-08-17

申请人： Eli Lusky ,  Boaz Eitan

发明人： Eli Lusky ,  Boaz Eitan

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445

摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

摘要翻译： 一种方法包括确定要一起擦除的行组，以便在大量程序和擦除循环之后最小化与烘烤相关的裕度损失。 该方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，将这些组擦除在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤 以前没有擦除验证。

公开(公告)号：US20070041249A1

公开(公告)日：2007-02-22

申请号：US11205716

申请日：2005-08-17

申请人： Eli Lusky ,  Boaz Eitan

发明人： Eli Lusky ,  Boaz Eitan

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445

摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

摘要翻译： 一种方法包括确定要一起擦除的行组，以便在大量程序和擦除循环之后最小化与烘烤相关的裕度损失。 该方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，将这些组擦除在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤 以前没有擦除验证。

公开(公告)号：US07123532B2

公开(公告)日：2006-10-17

申请号：US11194394

申请日：2005-08-01

申请人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen

发明人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen

IPC分类号： G11C7/02

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5634

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

摘要翻译： 一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位 相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。 与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

公开(公告)号：US06954393B2

公开(公告)日：2005-10-11

申请号：US10662535

申请日：2003-09-16

申请人： Eli Lusky ,  Boaz Eitan

发明人： Eli Lusky ,  Boaz Eitan

IPC分类号： G11C7/00 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C17/00

CPC分类号： G11C16/3427 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving the same sensing accuracy with improved read disturb immunity.

摘要翻译： 一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位 相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。 与现有技术相比，本发明可以实现具有改善的读取干扰抗扰度的相同感测精度。

公开(公告)号：US20050057953A1

公开(公告)日：2005-03-17

申请号：US10662535

申请日：2003-09-16

申请人： Eli Lusky ,  Boaz Eitan

发明人： Eli Lusky ,  Boaz Eitan

IPC分类号： G11C7/00 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C17/00

CPC分类号： G11C16/3427 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving the same sensing accuracy with improved read disturb immunity.

公开(公告)号：US20110122688A1

公开(公告)日：2011-05-26

申请号：US12926584

申请日：2010-11-29

申请人： Eli Lusky ,  Boaz Eitan

发明人： Eli Lusky ,  Boaz Eitan

IPC分类号： G11C16/28 ,  H01L21/8246

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5634

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

公开(公告)号：US20090231915A1

公开(公告)日：2009-09-17

申请号：US12292654

申请日：2008-11-24

申请人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen ,  Eduardo Maayan

发明人： Eli Lusky ,  Boaz Eitan ,  Guy Cohen ,  Eduardo Maayan

IPC分类号： G11C16/04 ,  G11C7/02 ,  G11C16/06 ,  H01L21/336

CPC分类号： G11C16/3436 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5634

摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

摘要翻译： 一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位 相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。 与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

公开(公告)号：US20070173017A1

公开(公告)日：2007-07-26

申请号：US11336093

申请日：2006-01-20

申请人： Boaz Eitan ,  Eli Lusky

发明人： Boaz Eitan ,  Eli Lusky

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for creating a non-volatile memory array includes generating removable mask columns to define bit lines, implanting bit lines into the substrate at least between the columns, depositing oxide filler over the bit lines, removing the mask columns, depositing a polysilicon layer over the array and etching the polysilicon layer into word lines. The polysilicon extends at least into spaces left behind by the removed mask columns. The method also includes performing a dual work integration doping after the word line patterning.

摘要翻译： 用于创建非易失性存储器阵列的方法包括产生可移除掩模列以限定位线，至少在列之间将位线注入衬底中，在位线上沉积氧化物填充物，去除掩模柱，沉积多晶硅层 阵列并将多晶硅层蚀刻成字线。 多晶硅至少延伸到被去除的掩模柱留下的空间中。 该方法还包括在字线图案化之后执行双工整合掺杂。