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    Method of programming non-volatile memory device
    33.
    发明申请
    Method of programming non-volatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US20090059671A1

    公开(公告)日：2009-03-05

    申请号：US12213425

    申请日：2008-06-19

    申请人： Sang-Jin Park ,  Kwang-soo Seol ,  Jung-hun Sung

    发明人： Sang-Jin Park ,  Kwang-soo Seol ,  Jung-hun Sung

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3454

    摘要： A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in the memory cell if the memory cell passes the verification using the first verification voltage. The memory cell may be verified using a second verification voltage greater than the first verification voltage after the perturbation pulse is applied.

    摘要翻译： 编程非易失性存储器件的方法可以包括执行第一编程操作，包括将程序电压施加到存储器单元并且使用第一验证电压来验证存储器单元。 如果存储器单元通过使用第一验证电压的验证，则可以将扰动脉冲施加到存储器单元以便于存储器单元中的电荷的热化。 可以在施加扰动脉冲之后使用大于第一验证电压的第二验证电压来验证存储器单元。

    Nonvolatile memory device and method of fabricating the same
    34.
    发明申请
    Nonvolatile memory device and method of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20090045455A1

    公开(公告)日：2009-02-19

    申请号：US12219465

    申请日：2008-07-23

    申请人： Kwang-soo Seol ,  Sang-jin Park ,  Sang-moo Choi ,  Hyo-sug Lee ,  Jung-hun Sung

    发明人： Kwang-soo Seol ,  Sang-jin Park ,  Sang-moo Choi ,  Hyo-sug Lee ,  Jung-hun Sung

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L29/4234 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/66833

    摘要： Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking insulation film may be an aluminum oxide having an energy band gap larger than that of a γ-phase aluminum oxide film. An α-phase crystalline aluminum oxide film as a blocking insulation film may have an energy band gap of about 7.0 eV or more along with fewer defects. The crystalline aluminum oxide film may be formed by providing a source film (e.g., AlF3 film) on or within a preliminary blocking insulation film (e.g., amorphous aluminum oxide film) and performing a heat treatment. Alternatively, an aluminum compound (e.g., AlF3) may be introduced into the preliminary blocking insulation film by other diffusion methods or ion implantation. Accordingly, the ability of the memory device to maintain electric charges may be improved, the operating voltage for programming and erasing may be lowered, and the operating speed may be increased.

    摘要翻译： 示例性实施例涉及使用电荷存储层作为存储节点的非易失性半导体存储器件及其制造方法。 电荷阱型非易失性存储器件可以包括隧穿膜，电荷存储层，阻挡绝缘膜和栅电极。 阻挡绝缘膜可以是具有比γ相氧化铝膜的能带隙大的能带隙的氧化铝。 作为阻挡绝缘膜的α相结晶氧化铝膜可以具有约7.0eV以上的能带隙和更少的缺陷。 结晶氧化铝膜可以通过在预先隔离绝缘膜（例如无定形氧化铝膜）上或内部提供源膜（例如，AlF 3膜）并进行热处理而形成。 或者，可以通过其它扩散方法或离子注入将铝化合物（例如，AlF 3）引入到初步阻挡绝缘膜中。 因此，可以提高存储器件保持电荷的能力，可以降低用于编程和擦除的操作电压，并且可以提高操作速度。

    Semiconductor memory device including recessed control gate electrode
    36.
    发明申请
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US20080093662A1

    公开(公告)日：2008-04-24

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same
    37.
    发明申请
    Semiconductor memory device having an alloy metal gate electrode and method of manufacturing the same 审中-公开
    具有合金金属栅电极的半导体存储器件及其制造方法

    公开(公告)号：US20070190721A1

    公开(公告)日：2007-08-16

    申请号：US11655180

    申请日：2007-01-19

    申请人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    发明人： Young-kwan Cha ,  Young-soo Park ,  Kwang-soo Seol ,  Sang-jin Park ,  Sang-min Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/28088 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    摘要： A semiconductor memory device having an alloy gate electrode layer and method of manufacturing the same are provided. The semiconductor memory device may include a semiconductor substrate having a first impurity region and a second impurity region. The semiconductor memory device may include a gate structure formed on the semiconductor substrate and contacting the first and second impurity regions. The gate structure may include an alloy gate electrode layer formed of a first metal and a second metal. The first metal may be a noble metal. The second metal may include at least one of aluminum (Al) and titanium (Ti), gallium (Ga), indium (In), tin (Sb), thallium (Tl), bismuth (Bi) and lead (Pb).

    摘要翻译： 提供了具有合金栅电极层的半导体存储器件及其制造方法。 半导体存储器件可以包括具有第一杂质区和第二杂质区的半导体衬底。 半导体存储器件可以包括形成在半导体衬底上并与第一和第二杂质区接触的栅极结构。 栅极结构可以包括由第一金属和第二金属形成的合金栅极电极层。 第一种金属可能是贵金属。 第二金属可以包括铝（Al）和钛（Ti），镓（Ga），铟（In），锡（Sb），铊（Tl），铋（Bi）和铅（Pb）中的至少一种。

    Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions
    38.
    发明申请
    Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions 有权
    具有存储单元晶体管的非易失性存储器件具有较低的带隙源/漏区

    公开(公告)号：US20110233610A1

    公开(公告)日：2011-09-29

    申请号：US12974542

    申请日：2010-12-21

    申请人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

    发明人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

    IPC分类号： H01L29/772

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.

    摘要翻译： 非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。 源极/漏极区域可以与沟道区域形成非整流结。 源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same
    39.
    发明授权
    Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same 有权
    用于电荷陷阱半导体存储器件的电荷陷阱层及其制造方法

    公开(公告)号：US07795159B2

    公开(公告)日：2010-09-14

    申请号：US11987425

    申请日：2007-11-30

    申请人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    发明人： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

    IPC分类号： H01L21/31

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  Y10T428/31678

    摘要： Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

    摘要翻译： 提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。 该方法包括：（a）在待沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱 具有金属杂质在绝缘材料中隔离的结构的层。

    Methods of operating memory devices
    40.
    发明申请
    Methods of operating memory devices 有权
    操作存储设备的方法

    公开(公告)号：US20100008136A1

    公开(公告)日：2010-01-14

    申请号：US12458294

    申请日：2009-07-08

    申请人： Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

    发明人： Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621

    摘要： Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage.

    摘要翻译： 提供了操作NAND非易失性存储器件的方法。 操作方法包括从单元串的多个存储单元中向所选存储单元施加读取电压或验证电压以验证或读取所选存储单元的编程状态; 对最靠近所述单元串的选定存储单元的未选择存储单元施加第一通过电压; 将第二通过电压施加到所选择的存储器单元的第二最近的未选择的存储器单元; 以及向其他未选择的存储单元施加第三通过电压，其中第一通过电压小于第二和第三通过电压中的每一个，并且第二通过电压大于第三通过电压。