利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

141 条记录 (耗时 0.033 秒)

    Priority arbitration based on current task and MMU
    31.
    发明授权
    Priority arbitration based on current task and MMU 有权
    基于当前任务和MMU的优先仲裁

    公开(公告)号：US07120715B2

    公开(公告)日：2006-10-10

    申请号：US09932866

    申请日：2001-08-17

    申请人： Gerard Chauvel ,  Dominique D'Inverno

    发明人： Gerard Chauvel ,  Dominique D'Inverno

    IPC分类号： G06F13/14

    CPC分类号： G06F12/1027 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F9/5094 ,  G06F9/52 ,  G06F12/0292 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2209/5014 ,  G06F2209/5021 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/22 ,  Y02D10/24

    摘要： A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU. The arbitration circuitry is operable to schedule access to the shared resource according to higher of the pair of priority values provided by each processor.

    摘要翻译： 提供了数字系统和操作方法，其中若干处理器（740（0）-704（n））连接到共享资源（750）。 每个处理器具有通过在处理器上执行的软件加载访问优先级值的访问优先级寄存器（1410）。 存储器管理单元（MMU）（700）被连接以从每个相应的处理器接收请求地址（742）。 MMU具有一组对应于地址空间页面的条目。 每个条目为相关联的地址空间页面提供一组属性，包括地址空间优先级值309a。 对于每个请求，MMU访问与请求地址相对应的条目，并提供与该请求的地址空间页相关联的地址空间优先级值。 连接仲裁电路（1430），从每个处理器接收来自每个访问优先级寄存器的访问优先级值和来自每个MMU的地址空间优先级值的请求信号。 仲裁电路可操作以根据由每个处理器提供的优先级对中的较高者调度对共享资源的访问。

    Processor with a split stack
    32.
    发明授权
    Processor with a split stack 有权
    处理器与分离堆栈

    公开(公告)号：US07058765B2

    公开(公告)日：2006-06-06

    申请号：US10632079

    申请日：2003-07-31

    申请人： Gerard Chauvel ,  Maija Kuusela ,  Serge Lasserre

    发明人： Gerard Chauvel ,  Maija Kuusela ,  Serge Lasserre

    IPC分类号： G06F12/08

    CPC分类号： G06F9/30134 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30174 ,  G06F9/3879 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/1036 ,  G06F12/126 ,  G06F2212/502 ,  G06F2212/681 ,  Y02D10/13

    摘要： Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.

    摘要翻译： 公开了用于实现具有分组堆栈的处理器的方法和装置。 在一些实施例中，处理器包括主堆栈和微堆栈。 微堆优选地实现在处理器的核心中，而主堆栈可以在处理器核心外部的区域中实现。 操作数优选地通过微栈提供给算术逻辑单元（ALU），并且在下溢（微堆空）的情况下，可以从主堆栈获取操作数。 在溢出（微型堆栈完整）或通过显式冲洗微型堆栈时，操作数将写入主堆栈。 通过优化微堆栈的大小，可以减少从主堆栈取出的操作数的数量，从而可以降低处理器的功耗。

    Memory access instruction with optional error check
    35.
    发明申请
    Memory access instruction with optional error check 审中-公开
    内存访问指令，可选错误检查

    公开(公告)号：US20060026396A1

    公开(公告)日：2006-02-02

    申请号：US11116893

    申请日：2005-04-28

    申请人： Jean-Philippe Lesot ,  Gerard Chauvel

    发明人： Jean-Philippe Lesot ,  Gerard Chauvel

    IPC分类号： G06F9/00

    CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012 ,  Y02D10/13

    摘要： A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler. However, if the source register contents differs from the predetermined value, the load instruction causes the processor to cause a data value from memory to be loaded into a destination register

    摘要翻译： 处理器执行允许执行可选错误检查的加载（或存储）指令。 基于加载指令中的控制位，处理器通过使源寄存器的内容与预定值进行比较来执行加载指令。 如果源寄存器的内容等于预定值，则处理器执行异常处理程序。 然而，如果源寄存器内容与预定值不同，则加载指令使处理器将来自存储器的数据值加载到目的寄存器

    Automatic operand load and store
    36.
    发明申请
    Automatic operand load and store 有权
    自动操作数加载和存储

    公开(公告)号：US20060026391A1

    公开(公告)日：2006-02-02

    申请号：US11188827

    申请日：2005-07-25

    申请人： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

    发明人： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

    IPC分类号： G06F9/30

    CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

    摘要： A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.

    摘要翻译： 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则代替单个指令处理一组指令，需要操作数的单个指令。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，并将操作数存储到第二存储单元以供指令组使用。

    Method and system for accessing indirect memories
    37.
    发明申请
    Method and system for accessing indirect memories 有权
    访问间接存储器的方法和系统

    公开(公告)号：US20060026370A1

    公开(公告)日：2006-02-02

    申请号：US11186271

    申请日：2005-07-21

    申请人： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

    发明人： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

    摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

    摘要翻译： 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。

    Interruptible an re-entrant cache clean range instruction
    39.
    发明授权
    Interruptible an re-entrant cache clean range instruction 有权
    中断缓存清除范围指令

    公开(公告)号：US06772326B2

    公开(公告)日：2004-08-03

    申请号：US10157576

    申请日：2002-05-29

    申请人： Gerard Chauvel ,  Serge Lasserre ,  Dominique D'Inverno

    发明人： Gerard Chauvel ,  Serge Lasserre ,  Dominique D'Inverno

    IPC分类号： G06F944

    CPC分类号： G06F9/4843 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F12/0842 ,  G06F12/0891

    摘要： A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.

    摘要翻译： 提供了一种数字系统和操作方法，其中提供了一种用于清洁由起始参数和结束参数指定的存储区域中的地址范围的方法。 根据程序计数器，可以以指令序列（800）执行中断清除指令（802）。 如果在执行干净指令期间接收到中断（804），干净指令的执行将在完成之前暂停。 执行上下文切换（810）后，中断服务（820）。 在从中断服务程序（830,834）返回时，通过将清除指令提供的开始参数和结束参数与执行期间使用的相应起始寄存器和结束寄存器的当前内容进行比较来恢复干净指令的执行 干净的说明。 如果相同，则使用起始寄存器和结束寄存器的当前内容恢复干净指令的执行。 如果不同，通过将清除指令提供的启动参数存储在起始寄存器中并通过将结束参数存储在结束寄存器中来重新启动干净指令的执行。 以这种方式，在上下文切换期间不需要保存附加上下文信息，以便允许清除指令是可中断的。 如果在不可中断指令期间发生中断，则在中断服务程序在下一条指令（803）开始执行之前，上下文切换和返回（830,832）之前完成指令。 执行一系列操作的其他指令也可以以类似的方式中断。

    Cache with selective write allocation
    40.
    发明授权
    Cache with selective write allocation 有权
    具有选择性写入分配的缓存

    公开(公告)号：US06769052B2

    公开(公告)日：2004-07-27

    申请号：US10157555

    申请日：2002-05-29

    申请人： Gerard Chauvel ,  Maija Kuusela ,  Dominique D'Inverno

    发明人： Gerard Chauvel ,  Maija Kuusela ,  Dominique D'Inverno

    IPC分类号： G06F1200

    CPC分类号： G06F12/0888 ,  G06F12/0804 ,  Y02D10/13

    摘要： A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages) is defined within an address space of a back-up memory associated with the cache and write allocation in the cache is defined on a page basis. Each TLB has a set of entries that correspond to pages of address space and each entry provides a write allocate attribute (550) for the associated page of address space. During operation of the system, software programs are executed and memory transactions are performed. A write allocate attribute signal (550) is provided with each write transaction request. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request. Write allocation in the cache memory is performed generally in accordance with the write allocate attribute signal. However, write allocation policy circuitry (560) is also provided and operates to refine the operation of the write allocation. Thus, the cache memory is responsive to the write policy circuitry such that write allocation is performed in a selective manner in accordance to the attribute signal for a first write policy state and write allocation is always performed in accordance to the attribute signal for a second write policy state.

    摘要翻译： 提供了数字系统和操作方法，其中多个处理器（590n）连接到共享高速缓存存储器资源（500）。 连接翻译后备缓冲器（TLB）（310n）以从每个相应的处理器接收请求虚拟地址。 在与高速缓存相关联的备份存储器的地址空间内定义一组地址区（页），并且以页为基础定义高速缓存中的写分配。 每个TLB具有对应于地址空间的页面的一组条目，并且每个条目为相关联的地址空间页面提供写入分配属性（550）。 在系统操作期间，执行软件程序并执行存储器事务。 写入分配属性信号（550）被提供有每个写事务请求。 以这种方式，属性信号响应于分配给包括写事务请求地址的地址区的写分配属性位的值。 通常根据写入分配属性信号来执行高速缓冲存储器中的写入分配。 然而，还提供了写分配策略电路（560）并且操作以改进写分配的操作。 因此，高速缓冲存储器响应于写策略电路，使得根据用于第一写策略状态的属性信号以选择的方式执行写分配，并且总是根据用于第二写的属性信号执行写分配 政策状态。