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公开(公告)号：US20090043995A1
公开(公告)日：2009-02-12
申请号：US12253448
申请日：2008-10-17
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： An apparatus and method for handling data cache misses out-of-order for asynchronous pipelines are provided. The apparatus and method associates load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译： 提供了一种用于处理数据高速缓存的装置和方法，其中异步管线的次序不正常。 该装置和方法将加载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。 加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。 由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。 当加载指令发出并看到其在负载表中的对应条目标记为“未命中”时，取消加载指令的发布效果，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时 所需数据被回收。
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32.发明授权Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines 失效用于处理数据高速缓存的装置和方法对于异步管线错过无序公开(公告)号：US07461239B2
公开(公告)日：2008-12-02
申请号：US11345922
申请日：2006-02-02
申请人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
发明人： Christopher M. Abernathy , Jeffrey P. Bradford , Ronald P. Hall , Timothy H. Heil , David Shippy
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
摘要翻译： 提供了处理异步管道数据高速缓存未命中的机制。 这些机制将负载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。 加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。 由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。 当加载指令发出并看到其在负载表中的相应条目标记为“未命中”时，发出加载指令的影响被取消，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时 所需数据被回收。
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33.发明授权Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group 失效管道具有分叉全局分支历史缓冲区，用于每个指令获取组索引分支历史表公开(公告)号：US07454602B2
公开(公告)日：2008-11-18
申请号：US11013148
申请日：2004-12-15
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch history table includes multiple entries, each entry is associated with one or more branch instructions. The GBH information from the GBH buffer can be used to index into the branch history table to obtain a branch prediction signal. In response to a fetch group of instructions, a fixed number of GBH bits is shifted into the GBH buffer. The number of GBH bits is the same regardless of the number of branch instructions within the fetch group of instructions. In addition, there is a unique bit pattern associated with the case of no taken branch in the fetch group, regardless of the number of not-taken branches of even if there are any branches in the fetch group.
摘要翻译： 公开了一种用于更新全局分支历史信息的方法和装置。 数据处理系统中的动态分支预测器包括全局分支历史（GBH）缓冲区和分支历史表。 GBH缓冲区包含一组最新分支指令的GBH信息。 分支历史表包括多个条目，每个条目与一个或多个分支指令相关联。 来自GBH缓冲器的GBH信息可以用于索引到分支历史表中以获得分支预测信号。 响应于取指令组，固定数量的GBH位被移入GBH缓冲器。 无论读取指令组中的分支指令数如何，GBH位数都是相同的。 另外，即使在取出组中有任何分支，也不管抽取分支的数目如何，与获取组中没有分支的情况相关联的唯一位模式。
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公开(公告)号：US09733943B2
公开(公告)日：2017-08-15
申请号：US13613175
申请日：2012-09-13
CPC分类号： G06F9/3806
摘要： A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken.
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公开(公告)号：US07861065B2
公开(公告)日：2010-12-28
申请号：US12118298
申请日：2008-05-09
CPC分类号： G06F9/3851 , G06F9/3885
摘要： A computer processor that includes a plurality of execution pipelines, each execution pipeline including a configuration of one or more execution units of the processor, each execution pipeline characterized by an execution pipeline type, each execution pipeline type determined according to the types of computer program instructions executed in each execution pipeline; a plurality of hardware threads of execution, each hardware thread including computer program instructions characterized by instruction types, each hardware thread including sequences of instructions of a same instruction type, the sequences interspersed with instructions of other types; and an instruction dispatcher capable of dispatching instructions preferentially during a predefined preference period from a preferred hardware thread to a particular execution pipeline in dependence upon whether the preferred hardware thread presents a sequence of instructions, ready for execution from the preferred hardware thread, of a type for execution in the particular execution pipeline.
摘要翻译： 一种包括多个执行流水线的计算机处理器，每个执行流水线包括处理器的一个或多个执行单元的配置，每个执行流水线的特征在于执行流水线类型，根据计算机程序指令的类型确定每个执行流水线类型 在每个执行管道中执行; 多个执行硬件线程，每个硬件线程包括由指令类型表征的计算机程序指令，每个硬件线程包括相同指令类型的指令序列，所述序列散布有其他类型的指令; 以及指令分派器，其能够根据优选硬件线程是否提供从优选硬件线程准备执行的指令序列，优先在预定义的优选时段内从优选硬件线程调度指令到特定执行流水线 用于在特定执行管道中执行。
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公开(公告)号：US20080130667A1
公开(公告)日：2008-06-05
申请号：US11564863
申请日：2006-11-30
申请人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
发明人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.
摘要翻译： 一种采用可扩展分布仲裁方案的系统，包括：通过环形拓扑互连的多个站，用于在多个站之间传送数据; 以及耦合所述环形拓扑中的所述多个站的总线; 其中允许拓扑环上的多个站中的每一个通过评估一组输入来独立地决定何时将其数据加载到拓扑环上。
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