Abstract:
A face detector training method, a face detection method, and apparatuses are provided. In the present invention, during a training phase, a flexible block based local binary pattern feature and a corresponding second classifier are constructed, appropriate second classifiers are searched for to generate multiple first classifiers, and multiple layers of first classifiers that are obtained by using a cascading method form a final face detector; and during a detection phase, face detection is performed on a to-be-detected image by using a first classifier or a face detector that is learned during a training process, so that a face is differentiated from a non-face, and a face detection result is combined and output.
Abstract:
The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system.
Abstract:
A method and an apparatus for implementing compatibility of different processors are provided. The method includes: in a standby state of a board, obtaining configuration information and a type of a processor on the board; and if a processor type in the configuration information is different from the type of the processor, updating, according to the processor, a parameter that is relevant to the processor and is in the configuration information, and changing FLASH memory chip selection configuration in order to connect the connector to a FLASH memory for storing a BIOS program of the processor.