公开(公告)号：US06861940B2

公开(公告)日：2005-03-01

申请号：US10732053

申请日：2003-12-10

申请人： Nozomu Matsukawa ,  Akihiro Odagawa ,  Yasunari Sugita ,  Mitsuo Satomi ,  Yoshio Kawashima

发明人： Nozomu Matsukawa ,  Akihiro Odagawa ,  Yasunari Sugita ,  Mitsuo Satomi ,  Yoshio Kawashima

IPC分类号： G01R33/09 ,  H01F10/32 ,  H01C7/04

CPC分类号： H01L43/10 ,  B82Y25/00 ,  G01R33/093 ,  H01F10/324 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/3272

摘要： A magnetoresistive element of the present invention includes a multilayer structure that includes a non-magnetic layer (3) and a pair of ferromagnetic layers (1, 2) stacked on both sides of the non-magnetic layer (3). A resistance value differs depending on a relative angle between the magnetization directions of the ferromagnetic layers (1, 2) at the interfaces with the non-magnetic layer (3). The composition of at least one of the ferromagnetic layers (1, 2) in a range of 2 nm from the interface with the non-magnetic layer (3) is expressed by (MxOy)1-zZz, where Z is at least one element selected from the group consisting of Ru, Os, Rh, Ir, Pd, Pt, Cu, Ag, and Au, M is at least one element selected from the group consisting of elements other than Z and O and includes a ferromagnetic metal, and x, y, and z satisfy 0.33

摘要翻译： 本发明的磁阻元件包括层叠在非磁性层（3）的两侧的非磁性层（3）和一对铁磁体层（1,2）的多层结构体。 电阻值根据与非磁性层（3）的界面处的铁磁层（1,2）的磁化方向之间的相对角度而不同。 从与非磁性层（3）的界面在2nm范围内的铁磁层（1,2）中的至少一个的组成由（M×Oy）1-zZz表示，其中Z是至少一个元素 选自由Ru，Os，Rh，Ir，Pd，Pt，Cu，Ag和Au组成的组中的至少一种元素，M是选自Z和O以外的元素中的至少一种元素，并且包括铁磁性金属，以及 x，y和z满足0.33

公开(公告)号：US4823577A

公开(公告)日：1989-04-25

申请号：US153383

申请日：1988-02-08

申请人： Yoshio Kawashima ,  Shunji Ogata ,  Masaaki Yokoyama ,  Masato Tomiku ,  Tsuneo Yamada ,  Tsutomu Kuno ,  Hisao Murakami ,  Hiroyuki Morimoto ,  Toyoshige Myojo ,  Kozo Watanabe ,  Toshihiro Tanaka

发明人： Yoshio Kawashima ,  Shunji Ogata ,  Masaaki Yokoyama ,  Masato Tomiku ,  Tsuneo Yamada ,  Tsutomu Kuno ,  Hisao Murakami ,  Hiroyuki Morimoto ,  Toyoshige Myojo ,  Kozo Watanabe ,  Toshihiro Tanaka

IPC分类号： B21D43/02 ,  B21D43/09 ,  B21D43/28 ,  B21K27/02 ,  B23D33/00 ,  B21J7/46 ,  B21J1/06

CPC分类号： B23D33/006 ,  B21D43/021 ,  B21D43/09 ,  B21D43/285 ,  B21K27/02 ,  Y10T83/041 ,  Y10T83/283

摘要： Disclosed is a method and apparatus for feeding a material to a hot forging machine in a forging line in which a coiled material is uncoiled, straightened, fed intermittently by pinch rollers through a heating device, cut by a cutting device and then fed into a hot forging machine. The method has the steps of preparing a driving device which drives the pinch rollers mechanically independently from the hot forging machine; picking up the timing of forging conducted by the hot forging machine as an electric signal, and controlling the driving device in accordance with the electric signal.

公开(公告)号：US08537605B2

公开(公告)日：2013-09-17

申请号：US12867437

申请日：2009-02-09

申请人： Takumi Mikawa ,  Yoshio Kawashima ,  Koji Arita ,  Takeki Ninomiya

发明人： Takumi Mikawa ,  Yoshio Kawashima ,  Koji Arita ,  Takeki Ninomiya

IPC分类号： G11C11/14

CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.

摘要翻译： 非易失性半导体存储器件（100）包括设置有晶体管（101）的衬底（102）; 形成在所述衬底上以覆盖所述晶体管的第一层间绝缘层（103） 形成在所述第一层间绝缘层中并电连接到所述晶体管的漏电极（101a）或源电极（101b）中的任一个的第一接触插塞（104）和形成在所述第一中间层 绝缘层并与晶体管的漏电极或源电极中的另一个电连接; 形成为覆盖所述第一接触插塞的一部分的电阻变化层（106） 形成在电阻变化层上的第一线（107） 以及形成为覆盖所述第二接触插塞的一部分的第二线（108） 所述电阻变化层的端面与所述第一线的端面共面。

公开(公告)号：US20130140515A1

公开(公告)日：2013-06-06

申请号：US13810840

申请日：2012-02-22

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Ichirou Takahashi

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Ichirou Takahashi

IPC分类号： H01L45/00

CPC分类号： H01L45/1608 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1675

摘要： A method of manufacturing a nonvolatile memory element, the method including: forming a first lower electrode layer, a current steering layer, and a first upper electrode layer; forming a second lower electrode layer, a variable resistance layer, and a second upper electrode layer on the first upper electrode layer; patterning the second upper electrode layer, the variable resistance layer, and the lower electrode layer; patterning the first upper electrode layer, the current steering layer, and first lower electrode layer to form a current steering element, using the second lower electrode layer as a mask by use of etching which is performed on the second lower electrode layer at an etching rate lower than at least etching rates at which the second upper electrode layer and the variable resistance layer are etched; and forming a variable resistance element which has an area smaller than the area of the current steering element.

摘要翻译： 一种制造非易失性存储元件的方法，所述方法包括：形成第一下电极层，电流引导层和第一上电极层; 在所述第一上电极层上形成第二下电极层，可变电阻层和第二上电极层; 图案化第二上电极层，可变电阻层和下电极层; 对第一上电极层，电流引导层和第一下电极层进行构图，以形成电流导向元件，使用第二下电极层作为掩模，以蚀刻速率在第二下电极层上进行蚀刻 低于至少蚀刻第二上电极层和可变电阻层的蚀刻速率; 以及形成面积小于当前操舵元件面积的可变电阻元件。

公开(公告)号：US08445883B2

公开(公告)日：2013-05-21

申请号：US13126975

申请日：2009-07-16

申请人： Atsushi Himeno ,  Takumi Mikawa ,  Yoshio Kawashima

发明人： Atsushi Himeno ,  Takumi Mikawa ,  Yoshio Kawashima

IPC分类号： H01L29/02

CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.

摘要翻译： 提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。 非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70） 形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层 （78）通过选择性生长电镀形成。

公开(公告)号：US08389972B2

公开(公告)日：2013-03-05

申请号：US13129215

申请日：2010-09-13

申请人： Takumi Mikawa ,  Yoshio Kawashima

发明人： Takumi Mikawa ,  Yoshio Kawashima

IPC分类号： H01L29/02

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1675

摘要： To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage.The nonvolatile memory device (10) in the present invention includes: a lower electrode (105) formed above a substrate (100); a first variable resistance layer (106a) formed above the lower electrode (105) and comprising a transitional metal oxide; a second variable resistance layer (106b) formed above the first variable resistance layer (106a) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer (106a); and an upper electrode (107) formed above the second variable resistance layer (106b), wherein a step (106ax) is formed in an interface between the first variable is resistance layer (106a) and the second variable resistance layer (106b). The second variable resistance layer (106b) is formed covering the step (106ax) and has a bend (106bx) above the step (106ax).

摘要翻译： 通过降低断开电压以实现电阻变化并抑制断开电压的变化来实现存储器的小型化和增加的容量。 本发明的非易失性存储器件（10）包括：形成在衬底（100）上方的下电极（105）; 形成在所述下电极（105）上方并且包含过渡金属氧化物的第一可变电阻层（106a） 形成在第一可变电阻层（106a）上方的第二可变电阻层（106b），并且包括具有比第一可变电阻层（106a）的过渡金属氧化物高的氧含量的过渡金属氧化物; 以及形成在所述第二可变电阻层（106b）上方的上电极（107），其中在所述第一可变电阻层（106a）和所述第二可变电阻层（106b）之间的界面中形成台阶（106ax）。 第二可变电阻层（106b）被形成为覆盖台阶（106ax）并且在台阶（106ax）上方具有弯曲部（106bx）。

公开(公告)号：US08344345B2

公开(公告)日：2013-01-01

申请号：US12810667

申请日：2008-12-26

申请人： Takumi Mikawa ,  Yoshio Kawashima ,  Ryoko Miyanaga

发明人： Takumi Mikawa ,  Yoshio Kawashima ,  Ryoko Miyanaga

IPC分类号： H01L29/02

CPC分类号： H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).

摘要翻译： 包括第一存储器线（12）的第一布线层（19）通过穿过第一层间绝缘层（13）的第一触点（21）连接到包括第二存储器布线（17）的第二布线层（20）。 第一导线层（13）经由连接到第二导线层（20）并穿过第二层间绝缘层（18）的第二触点（26）连接并引出到上导线（22）。 第一触点（21）穿透第二导线层（20）的半导体层（17b）或绝缘体层（17c）。

公开(公告)号：US20110220862A1

公开(公告)日：2011-09-15

申请号：US13128575

申请日：2010-07-12

申请人： Koji Arita ,  Takumi Mikawa ,  Atsushi Himeno ,  Yoshio Kawashima ,  Kenji Tominaga

发明人： Koji Arita ,  Takumi Mikawa ,  Atsushi Himeno ,  Yoshio Kawashima ,  Kenji Tominaga

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666 ,  H01L45/1675

摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.

摘要翻译： 在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2）， 在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触 彼此仅在更靠近基板的通孔的开口（20）中。

公开(公告)号：US20110220861A1

公开(公告)日：2011-09-15

申请号：US13126975

申请日：2009-07-16

申请人： Atsushi Himeno ,  Takumi Mikawa ,  Yoshio Kawashima

发明人： Atsushi Himeno ,  Takumi Mikawa ,  Yoshio Kawashima

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.

摘要翻译： 提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。 非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70） 形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），并分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层 （78）通过选择性生长电镀形成。

公开(公告)号：US06943041B2

公开(公告)日：2005-09-13

申请号：US10719412

申请日：2003-11-21

申请人： Yasunari Sugita ,  Akihiro Odagawa ,  Nozomu Matsukawa ,  Yoshio Kawashima ,  Yasunori Morinaga

发明人： Yasunari Sugita ,  Akihiro Odagawa ,  Nozomu Matsukawa ,  Yoshio Kawashima ,  Yasunori Morinaga

IPC分类号： G01R33/09 ,  G11B5/39 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/093 ,  G11B5/3903 ,  G11B5/3909 ,  G11B5/3916 ,  G11B2005/3996 ,  G11C11/16 ,  H01F10/3254 ,  H01F10/3268 ,  H01F41/302 ,  H01L43/08 ,  H01L43/12

摘要： The present invention provides a method for producing a magnetoresistive element including a tunnel insulating layer, and a first magnetic layer and a second magnetic layer that are laminated so as to sandwich the tunnel insulating layer, wherein a resistance value varies depending on a relative angle between magnetization directions of the first magnetic layer and the second magnetic layer. The method includes the steps of: (i) laminating a first magnetic layer, a third magnetic layer and an Al layer successively on a substrate; (ii) forming a tunnel insulating layer containing at least one compound selected from the group consisting of an oxide, nitride and oxynitride of Al by performing at least one reaction selected from the group consisting of oxidation, nitriding and oxynitriding of the Al layer; and (iii) forming a laminate including the first magnetic layer, the tunnel insulating layer and a second magnetic layer by laminating the second magnetic layer in such a manner that the tunnel insulating layer is sandwiched by the first magnetic layer and the second magnetic layer. The third magnetic layer has at least one crystal structure selected from the group consisting of a face-centered cubic crystal structure and a face-centered tetragonal crystal structure and is (111) oriented parallel to a film plane of the third magnetic layer. According to this production method, it is possible to produce a magnetoresistive element with excellent properties and thermal stability.

摘要翻译： 本发明提供了一种制造磁阻元件的方法，该磁阻元件包括隧道绝缘层，以及第一磁性层和第二磁性层，其被层压以夹住隧道绝缘层，其中电阻值根据相对角度而变化 第一磁性层和第二磁性层的磁化方向。 该方法包括以下步骤：（i）在衬底上依次层叠第一磁性层，第三磁性层和Al层; （ii）通过进行选自Al层的氧化，氮化和氮氧化的至少一种反应，形成包含至少一种选自Al的氧化物，氮化物和氮氧化物的化合物的隧道绝缘层; 以及（iii）通过层叠所述第二磁性层来形成包括所述第一磁性层，所述隧道绝缘层和第二磁性层的层压体，使得所述隧道绝缘层被所述第一磁性层和所述第二磁性层夹在中间。 第三磁性层具有至少一种选自面心立方晶体结构和面心四边形晶体结构的晶体结构，并且（111）取向为平行于第三磁性层的膜平面。 根据该制造方法，可以制造出具有优异性能和热稳定性的磁阻元件。