公开(公告)号：US5781479A

公开(公告)日：1998-07-14

申请号：US853713

申请日：1997-05-09

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5719809A

公开(公告)日：1998-02-17

申请号：US694599

申请日：1996-08-09

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5615155A

公开(公告)日：1997-03-25

申请号：US582906

申请日：1996-01-04

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5477486A

公开(公告)日：1995-12-19

申请号：US408283

申请日：1995-03-22

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5475636A

公开(公告)日：1995-12-12

申请号：US294404

申请日：1994-08-23

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C11/40 ,  G11C13/00

CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5424981A

公开(公告)日：1995-06-13

申请号：US294403

申请日：1994-08-23

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US20080225883A1

公开(公告)日：2008-09-18

申请号：US12126259

申请日：2008-05-23

申请人： Mayuko TANAKA ,  Yoshimichi Kudo ,  Shigeto Oeda ,  Tadashi Kuwabara

发明人： Mayuko TANAKA ,  Yoshimichi Kudo ,  Shigeto Oeda ,  Tadashi Kuwabara

IPC分类号： H04L12/66

CPC分类号： H04L41/00 ,  H04L12/66

摘要： An object of the present invention is to provide network devices and a network device control method which enable control network devices connected to an IP network, AV devices connected over 1394IF through gateway devices from the IP network, and home devices connected to ECHONET to be controlled without distinction among them. To achieve this object, a network device to serve as a controller comprises a controller application that detects a service of a target network device, using a message complying with an information exchange protocol common to the network, collects information such as an access method for the service, a function name, and parameters, and controls the network device upon request, and an information exchange protocol processing part that exchanges messages according to a protocol common to the network devices. The network device targeted for control comprises service that provides information for the controlling network device to perform control to the controller, and the information exchange protocol processing part.

摘要翻译： 本发明的一个目的是提供一种网络设备和一种网络设备控制方法，其能够控制连接到IP网络的控制网络设备，通过来自IP网络的网关设备连接的1394IF的AV设备，以及连接到要被控制的ECHONET的家庭设备 他们之间没有区别。 为了实现该目的，用作控制器的网络设备包括使用符合网络公共信息交换协议的消息来检测目标网络设备的服务的控制器应用，收集诸如访问方法的信息 服务，功能名称和参数，并且根据请求控制网络设备，以及信息交换协议处理部分，其根据网络设备公用的协议来交换消息。 针对控制的网络设备包括向控制网络设备提供信息以对控制器执行控制的服务以及信息交换协议处理部分。

公开(公告)号：US06857131B1

公开(公告)日：2005-02-15

申请号：US08997487

申请日：1997-12-23

申请人： Yuichi Yagawa ,  Michio Morioka ,  Shigeki Hirasawa ,  Tadashi Kuwabara ,  Tomochika Ozaki ,  Akio Yajima

发明人： Yuichi Yagawa ,  Michio Morioka ,  Shigeki Hirasawa ,  Tadashi Kuwabara ,  Tomochika Ozaki ,  Akio Yajima

IPC分类号： G06F3/14 ,  G06F3/048 ,  G06F17/30 ,  G09G5/00 ,  H04N5/00 ,  H04N5/44 ,  H04N5/445 ,  H04N5/45 ,  H04N7/16 ,  H04N7/173 ,  H04N7/24 ,  H04N21/235 ,  H04N21/258 ,  H04N21/422 ,  H04N21/43 ,  H04N21/431 ,  H04N21/435 ,  H04N21/44 ,  H04N21/458 ,  H04N21/462 ,  H04N21/47 ,  H04N21/4722 ,  H04N21/4728 ,  H04N21/478 ,  H04N21/4782 ,  H04N21/81 ,  H04N21/858 ,  G06F13/00

CPC分类号： H04N21/4316 ,  H04N5/4401 ,  H04N5/445 ,  H04N5/44591 ,  H04N5/45 ,  H04N7/0122 ,  H04N21/235 ,  H04N21/25891 ,  H04N21/42204 ,  H04N21/4307 ,  H04N21/435 ,  H04N21/458 ,  H04N21/4622 ,  H04N21/47 ,  H04N21/4722 ,  H04N21/478 ,  H04N21/4782 ,  H04N21/812 ,  H04N21/858 ,  H04N21/8586

摘要： A device and method of displaying images and data on a display device. The device and method displays still and moving images in which at least one icon is associated and displayed with each image on a screen. A single screen may contain several images which change over time. As the images change so do the icons associated with them. Upon selection of an icon by a viewer, the device and method will display one of several possible advertisements or information associated with the icon. The selection of which advertisement or piece of information is based on information stored about the viewer. This information would include data concerning the viewer's age, income, address and hobbies. A list of selections made by a viewer is maintained and may be displayed at the viewer's request. The system may also force the display of advertisements if desired by advertisers.

摘要翻译： 一种在显示装置上显示图像和数据的装置和方法。 设备和方法显示静止图像和运动图像，其中至少一个图标与屏幕上的每个图像相关联并显示。 单个屏幕可能包含随时间变化的多个图像。 随着图像的改变，所以与他们相关联的图标。 在由观看者选择图标时，设备和方法将显示几个可能的广告之一或与图标相关联的信息。 选择哪个广告或信息是基于存储在关于观众的信息。 此信息将包括有关观众年龄，收入，地址和嗜好的数据。 维护观众所做的选择清单，并可根据观​​众的要求显示。 如果广告商需要，该系统还可以强制显示广告。

公开(公告)号：US5767864A

公开(公告)日：1998-06-16

申请号：US294405

申请日：1994-08-23

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G06F15/76

CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.

摘要翻译： 一种用于在显示装置的图形显示区域上显示像素数据的装置。 图形显示区域包括多个显示部分。 本发明包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及逻辑电路，用于对从存储器读出的一个像素数据的单位的组合进行逻辑运算 并提供给设备的外部数据。 逻辑电路基于逻辑运算输出像素数据，以便在显示装置的图形显示区域的一个显示部分上显示像素数据。

公开(公告)号：US5740369A

公开(公告)日：1998-04-14

申请号：US470219

申请日：1995-06-06

申请人： Tooru Yokozawa ,  Hiroshi Shimizu ,  Wataru Kitayama ,  Hidefumi Goto ,  Tadashi Kuwabara ,  Tomohiro Esaki ,  Yoshihiro Yamada

发明人： Tooru Yokozawa ,  Hiroshi Shimizu ,  Wataru Kitayama ,  Hidefumi Goto ,  Tadashi Kuwabara ,  Tomohiro Esaki ,  Yoshihiro Yamada

IPC分类号： G06F1/16 ,  G06F3/00 ,  G06F3/01 ,  G06Q20/12 ,  G07C9/02 ,  G07F7/00 ,  G07F17/16 ,  H04L12/28 ,  G06F15/40

CPC分类号： G06F3/016 ,  G06F1/1626 ,  G06F1/1684 ,  G06F1/1698 ,  G06F3/0485 ,  G06Q20/12 ,  G07C9/02 ,  G07F17/0014 ,  G07F17/16 ,  G06F2200/1614 ,  G06F2200/1637 ,  H04W8/26 ,  H04W88/02

摘要： A transmitting management apparatus transmits information having an identification number corresponding to a portable information terminal to which information is to be delivered and/or having a sorting code identifying the information. The portable information terminal receiving the transmitted information selectively acquires and stores proper information by referring to the identification number and/or the sorting code of the received information, and displays the proper information on a display means.

摘要翻译： 发送管理装置发送具有与要发送信息的便携式信息终端对应的识别号码和/或具有识别信息的分类码的信息。 接收发送信息的便携式信息终端通过参照接收到的信息的识别号码和/或分类代码选择性地获取并存储适当的信息，并且在显示装置上显示适当的信息。