公开(公告)号：US20170322905A1

公开(公告)日：2017-11-09

申请号：US15495933

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  SULEYMAN SAIR

IPC: G06F15/80 ,  G06F9/30

Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US20160179522A1

公开(公告)日：2016-06-23

申请号：US14581883

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： JESUS CORBAL ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

Abstract: An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; vector bit reversal logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the source vector register to generate a set of reversed bit groups; and a destination vector register to store the reversed bit groups.

Abstract translation: 用于执行向量比特反转的装置和方法。 例如，处理器的一个实施例包括：源向量寄存器，用于存储多个源位组，其中用于位组的大小将在指令的立即指定中; 矢量位反转逻辑，以从源向量寄存器内的邻近位组的立即和响应地反转位置确定位组大小，以产生一组反转位组; 以及存储反向位组的目的地向量寄存器。