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公开(公告)号：US20240219659A1
公开(公告)日：2024-07-04
申请号：US18089871
申请日：2022-12-28
Applicant: Intel Corporation
Inventor： Ziyin Lin , Yiqun Bai , Bohan Shan , Kyle Jordan Arrington , Haobo Chen , Dingying Xu , Robert Alan May , Gang Duan , Bai Nie , Srinivas Venkata Ramanuja Pietambaram
CPC classification number: G02B6/4246 , G02B5/10 , G02B6/4239 , H01Q1/2283
Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
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公开(公告)号：US20240203853A1
公开(公告)日：2024-06-20
申请号：US18085281
申请日：2022-12-20
Applicant: Intel Corporation
Inventor： Bohan Shan , Haobo Chen , Hongxia Feng , Julianne Troiano , Dingying Xu , Matthew Tingey , Xiaoying Guo , Srinivas Venkata Ramanuja Pietambaram , Bai Nie , Gang Duan , Bin Mu , Kyle Mcelhinny , Ashay A. Dani , Leonel R. Arana
IPC: H01L23/498 , H01L21/48 , H01L23/538
CPC classification number: H01L23/49827 , H01L21/4846 , H01L23/5384
Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.
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公开(公告)号：US20230197679A1
公开(公告)日：2023-06-22
申请号：US17558457
申请日：2021-12-21
Applicant: Intel Corporation
Inventor： Jeremy Ecton , Jason M. Gamba , Brandon C. Marin , Srinivas V. Pietambaram , Xiaoxuan Sun , Omkar G. Karhade , Xavier Francois Brun , Yonggang Li , Suddhasattwa Nad , Bohan Shan , Haobo Chen , Gang Duan
IPC: H01L25/065 , H01L23/00 , H01L23/538
CPC classification number: H01L25/0652 , H01L24/16 , H01L24/14 , H01L24/73 , H01L24/13 , H01L23/5383 , H01L2224/16227 , H01L2224/14177 , H01L2224/73204 , H01L2224/13111 , H01L2924/01079 , H01L2924/01047 , H01L2924/01029 , H01L2924/014 , H01L2924/01083 , H01L2924/01049 , H01L2924/01031
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.
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公开(公告)号：US20220199575A1
公开(公告)日：2022-06-23
申请号：US17126505
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Omkar G. Karhade , Bohan Shan
IPC: H01L25/065 , H01L23/538 , H01L23/00
Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
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公开(公告)号：US20220102259A1
公开(公告)日：2022-03-31
申请号：US17033392
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Jieying Kong , Yiyang Zhou , Suddhasattwa Nad , Jeremy Ecton , Hongxia Feng , Tarek Ibrahim , Brandon Marin , Zhiguo Qian , Sarah Blythe , Bohan Shan , Jason Steill , Sri Chaitra Jyotsna Chavali , Leonel Arana , Dingying Xu , Marcel Wall
IPC: H01L23/498 , H01L21/48
Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.
