公开(公告)号：US5015880A

公开(公告)日：1991-05-14

申请号：US419341

申请日：1989-10-10

申请人： Charles E. Drake ,  Howard L. Kalter ,  Scott C. Lewis

发明人： Charles E. Drake ,  Howard L. Kalter ,  Scott C. Lewis

IPC分类号： H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/00361 ,  H03K19/01721

摘要： A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：US5010524A

公开(公告)日：1991-04-23

申请号：US340962

申请日：1989-04-20

申请人： John A. Fifield ,  Howard L. Kalter

发明人： John A. Fifield ,  Howard L. Kalter

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C7/18

摘要： This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

公开(公告)号：US06429080B2

公开(公告)日：2002-08-06

申请号：US09793517

申请日：2001-02-27

申请人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

发明人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

IPC分类号： H01L21336

CPC分类号： G11C11/565 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10882

摘要： A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

摘要翻译： 能够存储两位或三位数字数据的多级存储器单元仅占用四个光刻平面，并且仅分别仅需要一个或两个逻辑电平电压源。 通过使用具有不同值的电容器，可以直接从施加到两个电容器的逻辑电平数字信号（以及八电平工作模式的位线）将存储单元中的多电平信号集成到高抗噪声性能 避免在写入过程中进行数模转换。 电容器可以同时写入和读取，以减少存储周期时间。 晶体管通道和电容器连接使用在柱之间的半导体材料的塞子作为公共栅极结构和连接形成在相邻的半导体柱上。 支柱的相对表面还用作具有通过塞子和柱之间的共形沉积形成的公共电容器板的存储节点。

公开(公告)号：US06282115B1

公开(公告)日：2001-08-28

申请号：US09469275

申请日：1999-12-22

申请人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

发明人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

IPC分类号： G11C1124

CPC分类号： G11C11/565 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10882

摘要： A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

摘要翻译： 能够存储两位或三位数字数据的多级存储器单元仅占用四个光刻平面，并且仅分别仅需要一个或两个逻辑电平电压源。 通过使用具有不同值的电容器，可以直接从施加到两个电容器的逻辑电平数字信号（以及八电平工作模式的位线）将存储单元中的多电平信号集成到高抗噪声性能 避免在写入过程中进行数模转换。 电容器可以同时写入和读取，以减少存储周期时间。 晶体管通道和电容器连接使用在柱之间的半导体材料的塞子作为公共栅极结构和连接形成在相邻的半导体柱上。 支柱的相对表面还用作具有通过塞子和柱之间的共形沉积形成的公共电容器板的存储节点。

公开(公告)号：US6114725A

公开(公告)日：2000-09-05

申请号：US93928

申请日：1998-06-09

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US5998868A

公开(公告)日：1999-12-07

申请号：US18736

申请日：1998-02-04

申请人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L21/762 ,  H01L21/98 ,  H01L23/13 ,  H01L25/065 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L25/50 ,  H01L21/7624 ,  H01L21/76264 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/81141 ,  H01L2224/83141 ,  H01L2224/97 ,  H01L29/0657 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15165

摘要： An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m

摘要翻译： 集成电路封装或布置包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。 相邻芯片的顶面基本上位于距离大于0.0μm的平面中。 相邻的芯片由间隙G分开，间距约为1μm〜约100μm。 金属互连设置在顶面和间隙之上。 优选地，互连在间隙上具有逐渐的斜率。

公开(公告)号：US5228046A

公开(公告)日：1993-07-13

申请号：US790797

申请日：1991-11-12

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级纠错能力，并且每个存储单元都与系统级错误校正功能相关联，通过提供用于禁用单位级错误校正的机制来增强存储器可靠性 能力，例如，响应于在一个存储器单元中发生不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

公开(公告)号：US5058115A

公开(公告)日：1991-10-15

申请号：US322255

申请日：1989-03-10

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Tin-Chee Lo

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Tin-Chee Lo

IPC分类号： G06F12/16 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：US4782250A

公开(公告)日：1988-11-01

申请号：US91565

申请日：1987-08-31

申请人： Robert D. Adams ,  Roy C. Flaker ,  Kenneth S. Gray ,  Howard L. Kalter

发明人： Robert D. Adams ,  Roy C. Flaker ,  Kenneth S. Gray ,  Howard L. Kalter

IPC分类号： H03K17/08 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948 ,  H03K17/04 ,  H03K17/687 ,  H03K19/096

CPC分类号： H03K19/0948 ,  H03K19/00315 ,  H03K19/01721 ,  H03K19/09429

摘要： A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor arranged in series with a second or pull-up P-channel transistor and a third P-channel transistor connected from the common point between the first and second transistors and the gate electrode of the first transistor. The first and second transistors are disposed between a data output terminal and a first voltage source having a supply voltage of a given magnitude, with the data output terminal also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor, disposed in a common N-well with the other P-channel transistors, is connected at its source to the first voltage source and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

公开(公告)号：US4506341A

公开(公告)日：1985-03-19

申请号：US387132

申请日：1982-06-10

申请人： Howard L. Kalter ,  Francis W. Wiedman

发明人： Howard L. Kalter ,  Francis W. Wiedman

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  H03K19/096 ,  H03K19/177

CPC分类号： G06F7/5057 ,  H03K19/096 ,  H03K19/1772

摘要： A programmable PLA circuit in which an interlaced AND/OR array is provided which has both common input and common output lines. Separate AND and OR functions are generated during two different timing intervals such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval and to provide the Exclusive-NOR of sum of product terms or the sum of the Exclusive-NOR of product terms during the second time interval.

摘要翻译： 可编程PLA电路，其中提供具有公共输入和公共输出线的隔行的AND / OR阵列。 在两个不同的定时间隔期间产生分离的AND和OR功能，使得两个逻辑阵列可以物理共享输入和输出电路元件。 描述了二进制加法器，其中在两个时间间隔期间将阵列输出线对被施加到相同的异或非电路，以在AND阵列时间间隔期间提供乘积项的Exclusive-NOR，并且提供总和的Exclusive-NOR 的产品术语或第二时间间隔内产品术语的“异或”的总和。