摘要:
A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.
摘要:
A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要:
Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.
摘要:
A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要:
An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要:
Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要:
A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要:
A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要:
A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.
摘要:
A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.