专利检索 ap:("Josephine M. Cheng" OR "Donald J. Haderle" OR "Richard W. Hedges" OR "Balakrishna R. Iyer" OR "Chandrasekaran Mohan" OR "Yun Wang") AND inv:"Balakrishna R. Iyer" 第 4 页

31.

发明授权
Method and apparatus for checksum address generation in a fail-safe modular memory 失效
标题翻译：在故障安全模块化存储器中生成校验和地址的方法和装置

公开(公告)号：US5007053A

公开(公告)日：1991-04-09

申请号：US278104

申请日：1988-11-30

申请人： Balakrishna R. Iyer , Daniel M. Dias , Yitzhak Dishon

发明人： Balakrishna R. Iyer , Daniel M. Dias , Yitzhak Dishon

IPC分类号： G06F12/16 , G06F3/06 , G06F11/10 , G11C29/00

CPC分类号： G06F11/1008 , G06F11/1028 , G06F11/1076 , G11C29/70

摘要： A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.