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38 条记录 (耗时 0.035 秒)

    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    33.
    发明授权
    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene 失效
    系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌

    公开(公告)号：US06500357B1

    公开(公告)日：2002-12-31

    申请号：US09538443

    申请日：2000-03-29

    申请人： Lee Luo ,  Claes H. Bjorkman ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin

    发明人： Lee Luo ,  Claes H. Bjorkman ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin

    IPC分类号： H01L21302

    CPC分类号： H01L21/67167 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/6723 ,  H01L21/76807

    摘要： An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to an oxygen plasma or similar environment to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in either the second or a third etching chamber of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps.

    摘要翻译： 在具有第一和第二蚀刻室的多室基板处理系统中执行的集成原位蚀刻工艺。 该工艺包括将在其上形成的衬底沿着向下的方向转印图案化的光致抗蚀剂掩模，介电层，停止层和衬底中的要接触第一蚀刻室的特征，以蚀刻电介质层。 然后在真空条件下将衬底从第一蚀刻室转移到第二蚀刻室，并且在第二蚀刻室中暴露于氧等离子体或类似环境以剥离沉积在衬底上的光致抗蚀剂掩模。 在剥离光致抗蚀剂掩模之后，将停止层蚀刻到要在多室基板处理系统的第二或第三蚀刻室中接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的，因此基板不会在台阶之间暴露于环境中。

    Methods and devices to reduce defects in dielectric stack structures
    34.
    发明授权
    Methods and devices to reduce defects in dielectric stack structures 失效
    减少电介质堆叠结构缺陷的方法和装置

    公开(公告)号：US07608300B2

    公开(公告)日：2009-10-27

    申请号：US10650941

    申请日：2003-08-27

    申请人： Christopher Dennis Bencher ,  Lee Luo

    发明人： Christopher Dennis Bencher ,  Lee Luo

    IPC分类号： C23C16/00 ,  B05D1/40 ,  H05H1/00 ,  H05H1/32

    CPC分类号： C23C16/4401 ,  C23C16/0245 ,  C23C16/56

    摘要： A variety of techniques may be employed alone or in combination to reduce the incidence of defects arising in dielectric stack structures formed by chemical vapor deposition (CVD). Incidence of a first defect type attributable to reaction between an unreacted species of a prior CVD step and reactants of a subsequent CVD step, is reduced by exposing a freshly-deposited dielectric layer to a plasma before any additional layers are deposited. Incidence of a second defect type attributable to the presence of incompletely vaporized CVD liquid precursor material, is reduced by exposing the freshly-deposited dielectric layer to a plasma, and/or by continuing the flow of carrier gas through an injection valve for a period beyond the conclusion of the CVD step.

    摘要翻译： 各种技术可以单独使用或组合使用以减少通过化学气相沉积（CVD）形成的介电堆叠结构中产生的缺陷的发生率。 通过在沉积任何另外的层之前将新沉积的介电层暴露于等离子体，可以减少归因于现有CVD步骤的未反应物质与随后的CVD步骤的反应物之间的反应的第一缺陷类型的发生。 归因于存在不完全蒸发的CVD液体前体材料的第二种缺陷类型的发生通过将新沉积的介电层暴露于等离子体和/或通过使载气通过喷射阀的流动持续一段时间来减少 CVD步骤的结论。

    Methods and devices to reduce defects in dielectric stack structures
    35.
    发明申请
    Methods and devices to reduce defects in dielectric stack structures 审中-公开
    减少电介质堆叠结构缺陷的方法和装置

    公开(公告)号：US20080257864A1

    公开(公告)日：2008-10-23

    申请号：US12082494

    申请日：2008-04-10

    申请人： Christopher Dennis Bencher ,  Lee Luo

    发明人： Christopher Dennis Bencher ,  Lee Luo

    IPC分类号： B44C1/22 ,  B05C11/02 ,  C23F1/08

    CPC分类号： C23C16/4401 ,  C23C16/0245 ,  C23C16/56

    摘要： A variety of techniques may be employed alone or in combination to reduce the incidence of defects arising in dielectric stack structures formed by chemical vapor deposition (CVD). Incidence of a first defect type attributable to reaction between an unreacted species of a prior CVD step and reactants of a subsequent CVD step, is reduced by exposing a freshly-deposited dielectric layer to a plasma before any additional layers are deposited. Incidence of a second defect type attributable to the presence of incompletely vaporized CVD liquid precursor material, is reduced by exposing the freshly-deposited dielectric layer to a plasma, and/or by continuing the flow of carrier gas through an injection valve for a period beyond the conclusion of the CVD step.

    摘要翻译： 各种技术可以单独使用或组合使用以减少通过化学气相沉积（CVD）形成的介电堆叠结构中产生的缺陷的发生率。 通过在沉积任何另外的层之前将新沉积的介电层暴露于等离子体，可以减少归因于现有CVD步骤的未反应物质与随后的CVD步骤的反应物之间的反应的第一缺陷类型的发生。 归因于存在不完全蒸发的CVD液体前体材料的第二种缺陷类型的发生通过将新沉积的介电层暴露于等离子体和/或通过使载气通过喷射阀的流动持续一段时间来减少 CVD步骤的结论。

    Methods for silicon oxide and oxynitride deposition using single wafer low pressure CVD
    38.
    发明授权
    Methods for silicon oxide and oxynitride deposition using single wafer low pressure CVD 有权
    使用单晶片低压CVD的氧化硅和氮氧化物沉积方法

    公开(公告)号：US06713127B2

    公开(公告)日：2004-03-30

    申请号：US10041026

    申请日：2001-12-28

    申请人： Janardhanan Anand Subramony ,  Yoshitaka Yokota ,  Ramaseshan Suryanarayanan Iyer ,  Lee Luo ,  Aihua Chen

    发明人： Janardhanan Anand Subramony ,  Yoshitaka Yokota ,  Ramaseshan Suryanarayanan Iyer ,  Lee Luo ,  Aihua Chen

    IPC分类号： C23C1640

    CPC分类号： C23C16/45512 ,  C23C16/308 ,  C23C16/401 ,  C23C16/56

    摘要： An oxide and an oxynitride films and their methods of fabrication are described. The oxide or the oxynitride film is grown on a substrate that is placed in a deposition chamber. A silicon source gas (or a silicon source gas with a nitridation source gas) and an oxidation source gas are decomposed in the deposition chamber using a thermal energy source. A silicon oxide (or an oxynitride) film is formed above the substrate wherein total pressure for the deposition chamber is maintained in the range of 50 Torr to 350 Torr and wherein a flow ratio for the silicon source gas (or the silicon source gas with the nitridiation source gas) and the oxidation source gas is in the range of 1:50 to 1:10000 during a deposition process.

    摘要翻译： 描述了氧化物和氧氮化物膜及其制造方法。 氧化物或氧氮化物膜在放置在沉积室中的衬底上生长。 使用热能源在沉积室中分解硅源气体（或具有氮化源气体的硅源气体）和氧化源气体。 在基板上方形成氧化硅（或氮氧化物）膜，其中沉积室的总压力保持在50Torr至350Torr的范围内，并且其中硅源气体（或硅源气体 氮化源气体），氧化源气体在沉积过程中为1:50至1：10000。