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37 条记录 (耗时 0.029 秒)

    Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
    31.
    发明申请
    Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates 有权
    通过边缘角优化固相外延的沟槽边缘缺陷重结晶：混合取向基板的方法和应用

    公开(公告)号：US20070241323A1

    公开(公告)日：2007-10-18

    申请号：US11406123

    申请日：2006-04-18

    申请人： Katherine Saenger ,  Chun-yung Sung ,  Haizhou Yin

    发明人： Katherine Saenger ,  Chun-yung Sung ,  Haizhou Yin

    IPC分类号： H01L31/00 ,  C30B21/04 ,  H01L29/04 ,  H01L29/10 ,  C30B28/14

    CPC分类号： H01L29/045 ,  C30B1/023 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203

    摘要： Edge-angle-optimized solid phase epitaxy is described as a method for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orientation of an underlying single-crystal Si template after an amorphization step. For the case of amorphized Si regions recrystallizing to (100) surface orientation, the trench-edge-defect-free recrystallization of edge-angle-optimized solid phase epitaxy may be achieved in rectilinear Si device regions whose edges align with the (100) crystal's in-plane directions. In a first aspect of the invention, twist-angle-optimized bonding and edge-angle-optimized epitaxy are applied to the fabrication of trench-edge-defect-free hybrid orientation substrates comprising (110)-oriented Si device regions in which high-performance p-channel field effect transistors (pFETs) may be formed and amorphized-and-recrystallized changed-orientation (100)-oriented Si device regions in which high-performance n-channel field effect transistors (nFETs) may be formed. In a second aspect of the invention, nFETs are fabricated in (100)-oriented Si regions in hybrid orientation substrates using edge-angle-optimized solid phase epitaxy to achieve trench-edge-defect-free amorphized-and-recrystallized source/drain regions.

    摘要翻译： 边缘角优化的固相外延被描述为用于形成混合定向衬底的方法，其包括当Si的沟槽分离区域被重结晶为底层单体的取向时通常看到的没有沟槽边缘缺陷的改变取向Si器件区域 非晶态Si模板。 对于非晶化Si区域重结晶到（100）表面取向的情况，边缘角优化固相外延的无边缘缺陷重结晶可以在其边缘与（100）晶体的边缘对齐的直线Si器件区域中实现 在平面<100>方向。 在本发明的第一方面中，将扭转角优化的结合和边缘角优化的外延应用于包括（110）取向的Si器件区域的无沟槽缺陷的混合取向衬底的制造， 可以形成高性能p沟道场效应晶体管（pFET）和可以形成高性能n沟道场效应晶体管（nFET）的非晶化和再结晶的改变取向（100）取向（100）取向的Si器件区域。 在本发明的第二方面中，使用边缘角优化的固相外延，在混合取向基板中的（100）取向的Si区域中制造nFET，以实现无沟槽边缘缺陷的非晶化和再结晶源极/漏极区域 。

    Mixed orientation and mixed material semiconductor-on-insulator wafer
    32.
    发明申请
    Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
    混合取向和混合材料绝缘体上半导体晶片

    公开(公告)号：US20070015346A1

    公开(公告)日：2007-01-18

    申请号：US11522905

    申请日：2006-09-19

    申请人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

    发明人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

    摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

    摘要翻译： 本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。 根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。 根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。 还公开了用于制造本发明的不同实施例的方法和过程。

    Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
    33.
    发明申请
    Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
    使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解

    公开(公告)号：US20060154442A1

    公开(公告)日：2006-07-13

    申请号：US11031165

    申请日：2005-01-07

    申请人： Joel de Souza ,  John Ott ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

    发明人： Joel de Souza ,  John Ott ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

    IPC分类号： H01L21/46

    CPC分类号： H01L21/187 ,  H01L21/76251

    摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.

    摘要翻译： 本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。 特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。 约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。 当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。 在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。 两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

    Field effect transistor with etched-back gate dielectric
    35.
    发明申请
    Field effect transistor with etched-back gate dielectric 有权
    具有蚀刻背栅电介质的场效应晶体管

    公开(公告)号：US20050127417A1

    公开(公告)日：2005-06-16

    申请号：US10730892

    申请日：2003-12-10

    申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/94

    CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

    摘要： A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.

    摘要翻译： 提供一种用于制造用于场效应晶体管的超薄高k栅极电介质的方法。 该方法包括在衬底上沉积高k栅极电介质材料，并通过对高k栅极电介质材料进行稀化处理来形成超薄高介电常数。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。 除了上述之外，本发明涉及一种用于通过上述方法制造的场效应晶体管的超薄高k栅极电介质。